LOCAL ROUTING NETWORK WITH SELECTIVE FAST PATHS FOR PROGRAMMABLE LOGIC DEVICE
A routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.
The present invention relates to programmable logic devices, and more specifically to routing networks used in programmable logic devices.
BACKGROUNDA programmable logic device, sometimes referred to as programmable application specific integrated circuit (PASIC), field programmable gate array (FPGA), or complex programmable logic device (CPLD), is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a programmable logic device, the user configures an on-chip interconnect structure of the programmable logic device so that selected input terminals and selected output terminals of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the specific circuit desired by the user.
Programmable logic devices include a number of programmable logic blocks that are interconnected by a programmable routing network, sometimes referred to as an interconnect network.
SUMMARYA routing network is associated with a logic island in a logic block of a programmable logic device and includes switches for each of feedback, street, and highway networks. Some of the switches include multiple stages. The street network switch receives the signals from the feedback network switch, signals from neighboring highway network switches, and direct feedback from selected logic island outputs and provides outputs to the logic island. The street network switch includes multiple stages, where outputs to the logic island are provided directly by each stage in the street network switch. The output terminals of a first stage of the street network switch that are connected to the logic island are also connected to the second stage of the street network switch. The second stage of the street network switch receives feedback output signals from the feedback network and directly from the associated logic island.
In one implementation, a programmable logic device includes a plurality of logic blocks and an interconnecting network; wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises: a network switch comprising a first stage of switch boxes and a second stage of switch boxes, wherein a first portion of output terminals of the first stage of switch boxes is connected directly to the logic island and is connected directly to a first set of input terminals of the second stage of switch boxes, and a second portion of output terminals of the first stage of switch boxes is connected to a second set of input terminals of the second stage of switch boxes.
In one implementation, a programmable logic device includes a plurality of logic blocks and an interconnecting network; wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises: a network switch comprising a first stage of switch boxes, a second stage of switch boxes connected to the first stage of switch boxes, and a third stage of switch boxes connected to the second stage of switch boxes, wherein a first portion of output terminals of the first stage of switch boxes is connected directly to the logic island, a first portion of output terminals of the second stage of switch boxes is connected directly to the logic island, and output terminals of the third stage of switch boxes is connected directly to the logic island.
In one implementation, a programmable logic device includes a plurality of logic blocks and an interconnecting network; wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises: a feedback network comprising a feedback network switch, the feedback network switch receiving a first set of output signals from the logic island and producing feedback output signals; and a street network comprising a street network switch, the street network switch comprising a first stage of switch boxes and a second stage of switch boxes connected to the first stage of switch boxes, wherein at least one switch box in the second stage of switch boxes has at least one input terminal coupled directly to the feedback network switch to receive the feedback output signals, and at least one switch box in the second stage of switch boxes has at least one input terminal coupled directly to the logic island to directly receive a second set of output signals from the logic island, wherein the set of output signals received by the second stage of switch boxes from the logic island does not pass through the feedback network switch.
The output terminals of the top LUT 202 and bottom LUT 204 are also coupled as inputs to 2×1 multiplexor 206. A select terminal of the multiplexor 206 is coupled to an input TBS. The multiplexor 206 produces a combinatorial logic signal on its output terminal 207. As illustrated, the input TBS is also coupled to an input terminal of the second 2×1 multiplexor 208 along with the output terminal 207 of multiplexor 206. The output terminal of the multiplexor 208 is coupled to the data D input of the register 210. The select terminal of the multiplexor 208 may be fixed, e.g., an SRAM-bit programmed at time of initiation of the programmable logic device to a tie high (VDD) signal or a tie low (GND) signal.
The register 210, illustrated as a D-type flip-flop, has a data D input terminal coupled to the output terminal of multiplexor 208, as well as a clock terminal driven by input QCK. The register 210 may further include a flip-flop enable input terminal E driven by input QEN, set signal input terminal driven by QST and reset signal input terminal driven by QRT. The register 210 includes an output terminal Q that is coupled to a first input terminal of the third 2×1multiplexor 212. As can be seen, the output terminal 207 of first multiplexor 206 may also be coupled to an input terminal of the third multiplexor 212. The select terminal of the multiplexor 212, thus, selects between the output of the register 210 and the output of the combinatorial logic provided by LUTs 202 and 204 and multiplexor 206. The output terminal of multiplexor 212 may be provided as output CQZ. The select terminal of the multiplexor 212 may be fixed, e.g., an SRAM-bit programmed at time of initiation of the programmable logic device to a tie high (VDD) signal or a tie low (GND) signal.
As illustrated in
As illustrated in
The qck mux 850, e.g., may be a 6:1 mux, that receives five clock signals (Clock<0:4>, as well as a sixth input S3 qck from the street network switch 500, e.g., which may be an output from the third stage of switches (S3). As illustrated, the clock network switch 800 may receive a subset of the clock signals, e.g., Clock<1:4>.
The feedback network switch 600 may receive at least a portion of the output data (logic out) from the logic island 400. For example, as illustrated in
Additionally, the feedback network switch 600 may receive Z-out signals from additional neighboring logic islands, e.g., four additional logic islands in logic blocks located diagonally with respect to the logic block 102. Thus, feedback network switch 600 may receive Z-out signals from a total of eight neighboring logic blocks. For example, the feedback network switch 600 may additionally receive Z-out signals from the diagonally neighboring logic blocks, including a Z-out signal from the four logic cells in a logic island to the immediate left-top (e.g., 1 ltZ-out), a Z-out signal from the four logic cells in a logic island to the immediate right-top (e.g., 1 rtZ-out), a Z-out signal from the four logic cells in a logic island to the immediate left-bottom (1 lbZ-out), and a Z-out signal from the four logic cells in a logic island to the immediate right-bottom (e.g., 1 rbZ-out). If desired, more than one Z-out signal may be received from each logic islands in immediately diagonally neighboring logic blocks and the Z-out signals may be, e.g., the CQZ outputs and/or the TZ outputs (if logic cells 200 shown in
Thus, in one implementation, the feedback network switch 600 receives a first type of Z-out signal, e.g., outputs BZ, from the local logic island 400, i.e., the logic island 400 associated with the feedback network switch 600, and the feedback network switch 600 receives a different type of Z-out signal, e.g., outputs CQZ, from the eight neighboring logic cells, e.g., neighboring logic islands in logic blocks to the sides and diagonals of the feedback network switch 600.
The feedback network switch 600 provides its output (feedback out) to the street network switch 500. The street network switch 500 also may receive at least a portion of the output data (logic out) from the logic island 400. For example, as illustrated in
The street network switch 500 may also receive clock signals from the clock network switch 800. The street network switch 500 also receives signals from a plurality of neighboring highway network switches, i.e., highway network switches in a plurality (i) of neighboring logic blocks in each direction, e.g., to the left (l), right (r), top (t) and bottom (b) with respect to the street network switch 500. For example, in one implementation, i=4, and thus, the street network switch 500 may receive signals from four neighboring highway network switches to the left li (i=1, 2, 3, 4), right ri (i=1, 2, 3, 4), top ti (i=1, 2, 3, 4), and bottom bi (i=1, 2, 3, 4). Thus, as illustrated in
Moreover, if desired, the street network switch 500 may additionally receive signals from a plurality of neighboring highway network switches in the diagonal directions with respect to logic block 102. For example, the street network switch 500 may receive signals from a plurality j of highway network switches in eight directions, including the left (l), right (r), top (t) and bottom (b), as well as the left-top (lt), right-top (rt), left-bottom (lb) and right-bottom (rb), where j may be the same or different than i. Thus, where j=4, street network switch 500 may receive additional signals from, e.g., the highway network switches associated with four neighboring logic blocks to the left-top (lt1, lt2, lt3, lt4), the highway network switches associated with four neighboring logic blocks to the right-top (rt1, rt2, rt3, rt4), the highway network switches associated with four neighboring logic blocks to the left-bottom (lb1,lb2,lb3,lb4), and the highway network switches associated with four neighboring logic blocks to the right-bottom (rb1, rb2, rb3, rb4).
The highway network switch 700 may also receive at least a portion of the output data (logic out) from the logic island 400. For example, as illustrated, the highway network switch 700 may receive 4×2 Z-out, as it may receive any of the two outputs from each of the four logic cells of the logic island 400 through local routing wires, e.g., the TZ outputs and the CQZ outputs from the four logic cells (if logic cells 200 shown in
Moreover, if desired, the highway network switch 700 may additionally receive signals from and output signals to a plurality of neighboring highway network switches in the diagonal directions with respect to logic block 102. For example,
The clock network switch 800 illustrated in
Feedback network resources 600a and 600b are coupled to the feedback network switch 600, where feedback network resources 600a are routing wires from the associated logic island outputs and feedback network resources 600b are routing wires from neighboring logic blocks, including diagonally neighboring logic blocks. Feedback network resources 600c are routing wires provided to neighboring logic blocks, including diagonally neighboring logic blocks and are also provided as street network resources 500a.
Highway network resources 700a and 700b are coupled to the highway network switch 700, where highway network resources 700a are routing wires coupled to the associated logic island outputs, and highway network resources 700b are routing wires from neighboring logic blocks, which are also coupled to the street network switch 500. As can be seen, some of the highway network resources 700a from the associated logic island outputs are provided to left, right, top and bottom neighboring logic blocks.
Thus, as illustrated logic island 400 provides output signals to the street network resources 500a, the feedback network resources 600a, 600c and the highway network resources 700a and the street network resources 500b and 500F provide inputs to the associated logic island 400. It can be seen that the feedback network resources 600b receive signals from the left, right, top and bottom and diagonally neighboring logic blocks, and the highway networks resources 700b receive signals from the left, right, top and bottom neighboring logic blocks. Additionally, the highway network switch 700 provides signals to left, right, top and bottom neighboring logic blocks.
The street network switch 500 is a Probabilistic Multistage Circuit Switching Network (PMCSN), which structurally differs from a conventional multi-stage non-blocking communication network topologies, such as a Clos network, as the street network switch 500 ensures just enough number of cross-points to meet a probabilistic goal in terms of possible number of paths through the stages for the class of circuits at interest. In a staged network system with a traditional multi-stage non-blocking communication network topologies, an input signal can reach an output without blocking any other signals. Thus, the reaching probability of any input signal to the output is 1. In PMCSN, on the other hand, while there are provisions for realizing any input at the outputs, there may be situations of simultaneous output demands of multiple input signals, and thus, blocking of one or more input signals is unavoidable in order to pass another input signal. The design of PMCSN emphasizes the non-blocking of signals that are determined to be higher in demand while signals that are lower in demand may be blocked. Consequently, probabilistically high demand signals will most likely be unblocked in PMCSN, which is why the street network switch 500 is probabilistic in nature.
As illustrated in
Additionally, as illustrated in
At least one switch box in stage S1 of the street network switch 500 includes at least one output terminal that does not have full access to all of the input terminals in that switch box. In one implementation, in each switch box 0-5 of stage S1, each output terminal 0-3 has access to less than all of the input terminals 0-15, e.g., half of the input terminals. For example, as indicated by “8:1” in each switch box in stage S1, each output terminal may have access to 8 of the 16 input terminals, e.g., via an 8×1 multiplexor, or other equivalent circuits, e.g., a 8×1 multiplexor may be replaced with a 7×1 multiplexor and a 2×1 multiplexor. Different output terminals in each switch box may have access to a different subset of the input terminals. Moreover, if desired, other sizes of proper subsets of the input terminals may be used and different output terminals may have access to a different number of input terminals. The specific input terminal that may be accessed by each output terminal may be programmed at time of initiation of the programmable logic device.
As illustrated in
Each switch box 0-3 in stage S2 may include a number of, e.g., 9, output terminals. A portion of the output terminals of each switch box 0-3 in stage S2 is connected directly to the input terminals of the switch boxes in the third stage S3. For example, 3 output terminals (labeled 3 S3) of each switch box 0-3 may be connected directly to the input terminals of the switch boxes in the third stage S3. The remaining portion of output terminals of each switch box 0-3 in stage S2, e.g., 6 output terminals of each switch box, may be connected directly to the logic island 400. By way of example, the output terminals from each switch box in second stage S2 that are connected directly to the logic island 400 may be connected to the input terminals of the LUTs in each logic cell, e.g., switch box 0 may have 6 output terminals directly connected to 6 LUT<0> inputs, switch box 1 may have 6 output terminals directly connected to 6 LUT<1> inputs, switch box 2 may have 6 output terminals directly connected to 6 LUT<2> inputs, and switch box 3 may have 6 output terminals directly connected to 6 LUT<3> inputs.
In one implementation, each output terminal has access to all of input terminals in each switch box in stage S2. For example, as indicated by “11:1” in each switch box in stage S2 in
The third stage S3 in the street network switch 500 also contains a plurality of switch boxes. By way of example, stage S3 is illustrated as containing 3 switch boxes (labeled 0-2), each having, e.g., 5 input terminals that are connected to 4 output terminals from the switch boxes 0-3 in stage S2 and the CLK signal. For example, as illustrated, the switch boxes 0-3 in stage S3 may each additionally include an input terminal that is connected to a portion of the output terminals from the clock network switch 800, shown in
The switch boxes 0-2 in stage S3 may have a number of output terminals, e.g., each switch box 0 and 2 in stage S3 is illustrated as having 4 output terminals and switch box 1 is illustrated with 3 output terminals. The output terminals from stage S3 are connected directly to the logic island 400, e.g., the different switch boxes in stage S3 may be coupled to different input terminals of the logic cells in the associated logic island. For example, the output terminals of switch box 0 in stage 3 may be received by the TBS input terminals in the logic cells, the output terminals of switch box 1 in stage 3 may be received by the QXX, i.e., any of the “Q” input terminals in the logic cells, and the output terminals of switch box 2 in stage 3 may be received by the QEN input terminals in the logic cells. As indicated by dots 502 in
In one implementation, each output terminal of each switch box in stage S3 may have access to all input terminals. For example, as indicated by “5:1” in each switch box in stage S3 in
The feedback network switch 600 is illustrated as a single stage S4 that includes a number of switch boxes in
Each switch box in stage S4 in the feedback network switch 600 may have four output terminals that are directly connected to input terminals of the switch boxes in stage S2 of the street network switch 500, as discussed above. In one implementation, each output terminal has access to less than all of the input terminals in each switch box in stage S4. For example, as indicated by “6:1” in each switch box in stage S4, each output terminal may have access to 6 out of the 8 input terminals, e.g., via a 6×1 multiplexor, or other equivalent circuits, e.g., a 6×1 multiplexor may be replaced with a 5×1 multiplexor and a 2×1 multiplexor. If desired, however, different output terminals in each switch box in stage S4 may have access to a different number of the input terminals. Moreover, if desired, other sizes of subsets of the input terminals may be used and different output terminals may have access to a different number of input terminals. The specific input terminal that may be accessed by each output terminal may be programmed at time of initiation of the programmable logic device.
By way of example, the highway network switch 700 may be similar to a Wilton switch structure, where some neighboring signals come from the immediate four neighbors and can take turn (i.e., change of direction) and one comes from the 4th neighbor that goes through without changing any direction. For routing fixed length wire segments are used, where the length is four units. In other words, a wire that originates from a highway network switch may travel to another highway network switch that is four highway network switches away, without turning. However, in order to provide the flexibility to connect the nearer highway network switches, the tapping from the wire at each unit length, i.e., at each highway network switch, is possible. Accordingly, signals may travel quickly to the most distant highway network switch as well reach a nearer highway network switch without creating substantial routing congestion.
Although the present invention is illustrated in connection with specific embodiments for instructional purposes, the present invention is not limited thereto. Various adaptations and modifications may be made without departing from the scope of the invention. For example, the number of specific input terminals, output terminals, and signals provided on each input terminal and output terminal may vary as desired. Moreover, while specific circuit elements, such as 7×1 multiplexors, are discussed, equivalent circuit elements, e.g., multiple multiplexors may be used. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description.
Claims
1. A programmable logic device comprising:
- a plurality of logic blocks and an interconnecting network;
- wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises:
- a network switch comprising a first stage of switch boxes and a second stage of switch boxes, wherein a first portion of output terminals of the first stage of switch boxes is connected directly to the logic island and is connected directly to a first set of input terminals of the second stage of switch boxes, and a second portion of output terminals of the first stage of switch boxes is connected to a second set of input terminals of the second stage of switch boxes.
2. The programmable logic device of claim 1, wherein at least a portion of output terminals of the second stage of switch boxes are connected to the logic island.
3. The programmable logic device of claim 1, wherein the logic island comprises a plurality of look-up tables, wherein the first portion of the output terminals of the first stage of switch boxes is connected directly to input terminals of the plurality of look-up tables.
4. The programmable logic device of claim 3, wherein output terminals of the second stage of switch boxes are connected to remaining input terminals of the plurality of look-up tables.
5. The programmable logic device of claim 1, wherein the network switch further comprises a third stage of switch boxes, wherein a first portion of output terminals of the second stage of switch boxes is connected directly to input terminals of the logic island, and a second portion of output terminals of the second stage of switch boxes is connected directly to input terminals of the third stage of switch boxes.
6. The programmable logic device of claim 5, wherein the first portion of the output terminals of the first stage of switch boxes is connected directly to a first set of input terminals of the logic island, the first portion of output terminals of the second stage of switch boxes is connected to a second set of input terminals of the logic island, and output terminals of the third stage of switch boxes are directly connected to a third set of input terminals of the logic island.
7. The programmable logic device of claim 5, wherein the network switch further receives clock signals, wherein one or more clock signals are provided to the logic island through one of the second stage of switch boxes or the third stage of switch boxes.
8. The programmable logic device of claim 1, wherein the routing network further comprises:
- a feedback network comprising a feedback network switch, the feedback network switch receiving a first set of output signals from the logic island and producing feedback output signals, wherein the feedback output signals are received by the second stage of the network switch.
9. The programmable logic device of claim 8, wherein input terminals of the second stage of switch boxes are directly connected to output terminals of the logic island to directly receive a set of feedback output signals from the logic island, wherein the set of feedback output signals received by the second stage of switch boxes does not pass through the feedback network switch.
10. The programmable logic device of claim 8, wherein the feedback network switch of the logic block further receives output signals from logic islands in neighboring logic blocks.
11. The programmable logic device of claim 10, wherein the neighboring logic blocks comprise logic blocks that are nearest to the logic block in top, bottom, right, and left directions.
12. The programmable logic device of claim 11, wherein the neighboring logic blocks further comprise logic blocks that are nearest to the logic block in top-left, top-right, bottom-left, and bottom-right diagonal directions.
13. The programmable logic device of claim 8, wherein the routing network further comprises:
- a highway network comprising a highway network switch, the highway network switch receiving a second set of output signals from the logic island, and receiving input signals from neighboring highway networks, the highway network switch providing output signals to the neighboring highway networks and neighboring street networks.
14. The programmable logic device of claim 13, wherein the neighboring highway networks comprise sets of highway networks that are adjacent to the logic block in top, bottom, right, and left directions.
15. The programmable logic device of claim 14, wherein each set of highway networks in each direction comprises at least four neighboring highway networks.
16. The programmable logic device of claim 13, wherein the network switch further receives the input signals from the neighboring highway networks.
17. The programmable logic device of claim 16, wherein the first stage of switch boxes in the network switch receives the input signals from the neighboring highway networks.
18. A programmable logic device comprising: a plurality of logic blocks and an interconnecting network;
- wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises:
- a network switch comprising a first stage of switch boxes, a second stage of switch boxes connected to the first stage of switch boxes, and a third stage of switch boxes connected to the second stage of switch boxes, wherein a first portion of output terminals of the first stage of switch boxes is connected directly to the logic island, a first portion of output terminals of the second stage of switch boxes is connected directly to the logic island, and output terminals of the third stage of switch boxes is connected directly to the logic island.
19. The programmable logic device of claim 18, wherein the first portion of output terminals of the first stage of switch boxes that is connected directly to the logic island is connected directly to a portion of input terminals of the second stage of switch boxes.
20. The programmable logic device of claim 18, wherein a first portion of output terminals of the second stage of switch boxes in the network switch is connected directly to the logic island, and a remaining portion of output terminals of the second stage of switch boxes is connected directly to input terminals of the third stage of switch boxes in the network switch.
21. The programmable logic device of claim 20, wherein the logic island comprises a plurality of look-up tables, wherein the first portion of output terminals of the second stage of switch boxes is connected to the input terminals of the plurality of look-up tables.
22. The programmable logic device of claim 18, wherein the network switch further receives clock signals, wherein the clock signals are provided to the logic island through at least one of the second stage of switch boxes and the third stage of switch boxes.
23. The programmable logic device of claim 18, wherein the routing network further comprises:
- a feedback network comprising a feedback network switch, the feedback network switch receiving a first set of output signals from the logic island and producing feedback output signals;
- wherein the second stage of switch boxes has a first set of input terminals that are coupled directly to the feedback network switch to receive the feedback output signals, a second set of input terminals that are coupled directly to output terminals of the first stage of switch boxes, and a third set of input terminals that are coupled directly to output terminals of the logic island.
24. The programmable logic device of claim 23, wherein the feedback network switch of the logic block further receives output signals from logic islands in neighboring logic blocks.
25. The programmable logic device of claim 24, wherein the neighboring logic blocks comprise logic blocks that are nearest to the logic block in top, bottom, right, and left directions.
26. The programmable logic device of claim 25, wherein the neighboring logic blocks further comprise logic blocks that are nearest to the logic block in top-left, top-right, bottom-left, and bottom-right diagonal directions.
27. The programmable logic device of claim 18, wherein the routing network further comprises:
- a highway network comprising a highway network switch, the highway network switch receiving a second set of output signals from the logic island, and receiving input signals from neighboring highway networks, the highway network switch providing output signals to the neighboring highway networks and to neighboring street networks.
28. The programmable logic device of claim 27, wherein the neighboring highway networks comprise sets of highway networks that are adjacent to the logic block in top, bottom, right, and left directions.
29. The programmable logic device of claim 28, wherein each set of highway networks in each direction comprises at least four highway networks.
30. The programmable logic device of claim 27, wherein the first stage of switch boxes of the network switch is coupled to receive the input signals from the neighboring highway networks.
31. A programmable logic device comprising:
- a plurality of logic blocks and an interconnecting network;
- wherein each logic block in the plurality of logic blocks comprises a logic island and a routing network associated with the logic island, wherein the routing network comprises:
- a feedback network comprising a feedback network switch, the feedback network switch receiving a first set of output signals from the logic island and producing feedback output signals; and
- a street network comprising a street network switch, the street network switch comprising a first stage of switch boxes and a second stage of switch boxes connected to the first stage of switch boxes, wherein at least one switch box in the second stage of switch boxes has at least one input terminal coupled directly to the feedback network switch to receive the feedback output signals, and at least one switch box in the second stage of switch boxes has at least one input terminal coupled directly to the logic island to directly receive a second set of output signals from the logic island, wherein the set of output signals received by the second stage of switch boxes from the logic island does not pass through the feedback network switch.
32. The programmable logic device of claim 31, wherein the street network further comprising a third stage of switch boxes connected to the second stage of switch boxes, wherein a first portion of output terminals of the second stage of switch boxes in the street network switch is connected directly to the logic island, and a second portion of output terminals of the second stage of switch boxes is connected directly to input terminals of the third stage of switch boxes in the street network switch.
33. The programmable logic device of claim 32, wherein the output terminals of the third stage of switch boxes in the street network switch are connected to a second set of input terminals of the logic island.
34. The programmable logic device of claim 33, wherein output terminals of the first stage of switch boxes in the street network switch is connected directly to input terminals of the second stage of switch boxes in the street network switch, and a portion of the output terminals of the first stage of switch boxes in the street network switch is connected directly to a third set of input terminals of the logic island.
35. The programmable logic device of claim 32, wherein the second stage and the third stage of the street network switch further receives clock signals, wherein the clock signals are provided to the logic island through at least one of the second stage of switch boxes and the third stage of switch boxes.
36. The programmable logic device of claim 31, wherein the feedback network switch of the logic block further receives output signals from logic islands in neighboring logic blocks.
37. The programmable logic device of claim 36, wherein the neighboring logic blocks comprise logic blocks that are nearest to the logic block in top, bottom, right, and left directions.
38. The programmable logic device of claim 37, wherein the neighboring logic blocks further comprise logic blocks that are nearest to the logic block in top-left, top-right, bottom-left, and bottom-right diagonal directions.
39. The programmable logic device of claim 31, wherein the routing network further comprises:
- a highway network comprising a highway network switch, the highway network switch receiving a third set of output signals from the logic island, and receiving input signals from neighboring highway networks, the highway network switch providing output signals to the neighboring highway networks and neighboring street networks.
40. The programmable logic device of claim 39, wherein the neighboring highway networks comprise sets of highway networks that are adjacent to the logic block in top, bottom, right, and left directions.
41. The programmable logic device of claim 40, wherein each set of highway networks in each direction comprises at least four neighboring highway networks.
42. The programmable logic device of claim 40, wherein the street network switch further receives the input signals from the neighboring highway networks.
43. The programmable logic device of claim 42 wherein the first stage of switch boxes in the street network switch receives the input signals from the neighboring highway networks.
Type: Application
Filed: Oct 1, 2015
Publication Date: Apr 6, 2017
Inventors: Pinaki Chakrabarti (Bangalore), Vishnu A. Patil (Bangalore), Wilma W. Shiao (San Jose, CA)
Application Number: 14/873,077