Abstract: The present disclosure provides embodiments of electronic fuse devices. An electronic fuse device according to the present disclosure includes a first bit cell comprising a first plurality of active regions extending along a first direction and a second bit cell comprising a second plurality of active regions extending along the first direction. Each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction. The first bit cell and the second bit cell are spaced apart along the first direction by a space and the space is free of a well tap cell.

Abstract: The present disclosure provides an integrated circuit (IC) structure that includes a semiconductor substrate having a frontside and a backside; a shallow trench isolation (STI) structure formed in the semiconductor substrate and defining an active region, wherein the STI structure includes a STI bottom surface, wherein the semiconductor substrate includes a substrate bottom surface, and wherein the STI bottom surface and the substrate bottom surface are coplanar; a field-effect transistor (FET) over the active region and formed on the frontside of the semiconductor substrate; and a backside dielectric layer disposed on the substrate bottom surface and the STI bottom surface.

Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.

Abstract: The present disclosure provides an IC structure that includes a semiconductor substrate having a SRAM region, an input/output and peripheral (IOP) region, and an edge region spanning tween the SRAM region and the IOP region; a STI structure formed on the semiconductor substrate and defining active regions; a SRAM cell formed within the SRAM region; and a backside dielectric layer disposed on a backside of the semiconductor substrate and landing on a bottom surface of the STI structure. The active regions are longitudinally oriented along a first direction; gates are formed on the semiconductor substrate and are evenly distributed with a pitch P along the first direction; the SRAM cell spans a first dimension Ds along the first direction; the edge region spans a second dimension De along the first direction; and a ratio De/Ds equals to 2 or is less than 2.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

Abstract: A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first active region in forming a first transistor. The second gate structure engages the second active region in forming a second transistor. The first and second transistors have a same conductivity type. The memory cell further includes a first epitaxial feature on a source region of the first transistor, a second epitaxial feature on a source region of the second transistor, a first frontside contact directly above and in electrical coupling with the first epitaxial feature, a second frontside contact directly above and in electrical coupling with the second epitaxial feature, and a first backside via directly under and in electrical coupling with one of the first and second epitaxial features with another one of the first and second epitaxial features free of a backside via directly thereunder.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively, and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. A first frontside source/drain contact is disposed above and electrically couples to a first common source/drain region of the first and second pull-down transistors. A first backside via is disposed under and electrically couples to the first common source/drain region. A first backside metal line is disposed under and electrically couples to the first backside via.

Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.

Abstract: Structures for a thermo-optic phase shifter and methods of forming a thermo-optic phase shifter. The structure comprises an interconnect structure including a dielectric layer, a waveguide core on the dielectric layer, and a heater on the dielectric layer. The heater includes a resistive heating element positioned adjacent to the waveguide core.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a functional cell region including an n-type functional transistor and a p-type functional transistor. The semiconductor structure also includes a first power transmission cell region including a first cutting feature and a first contact rail in the first cutting feature. The semiconductor structure also includes a first power rail electrically connected to a source terminal of the p-type functional transistor and the first contact rail of the first power transmission cell region. The semiconductor structure also includes a second power transmission cell region adjacent to the first power transmission cell and including a second cutting feature and second contact rail in the second cutting feature. The semiconductor structure also includes an insulating strip extending from the first cutting feature to the second cutting feature in a first direction.

Abstract: A memory cell includes first and second active regions and first and second gate structures. The first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull-up transistor, respectively. The second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively. The memory cell also includes a first source/drain contact via electrically coupled to the first and second pull-down transistors, a second source/drain contact via electrically coupled to the first and second pull-up transistors, a first gate contact electrically coupled to the first gate structure, and a second gate contact electrically coupled to the second gate structure. One of the first and second source/drain contact vias has an area larger than either of the first and second gate contacts in a top view of the memory cell.

Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

Abstract: A semiconductor structure includes a substrate, a fin-shaped structure protruding from the substrate and orienting lengthwise along a first direction, an isolation feature disposed over the substrate and along a sidewall of a bottom portion of the fin-shaped structure, and a metal gate structure disposed over the fin-shaped structure and the isolation feature and orienting lengthwise along a second direction perpendicular to the first direction. The metal gate structure includes a bottom portion sandwiched between the isolation feature and the bottom portion of the fin-shaped structure along the second direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure, a second fin structure, and a third fin structure over the substrate. Tops of the second fin structure and the third fin structure are at different height levels. The semiconductor device structure also includes a first epitaxial structure extending across sidewalls of the first fin structure and the second fin structure and a second epitaxial structure on the third fin structure. The first epitaxial structure is closer to the substrate than the second epitaxial structure.

Abstract: Account delegation is provided. A request for access to a secure system using an owner's account is received from an applier via a browser supplement module on the applier's computing device. The request is communicated to the account owner via a browser supplement module on the account owner's computing device. Approval of the request is received from the account owner. The secure system is logged into using the account owner's credential. A connection to the applier's computing device is established to act as a proxy for communication between the secure system and the applier's computing device. Further provided herein are a computer system and a computer program product for performing the method.

Abstract: Methods for manufacturing a semiconductor device structure are provided. The method includes forming a first masking layer covering a first region and a second region and forming a second masking layer over the first masking layer, and the second masking layer includes a first pattern over the second region. The method further includes forming a third masking layer over the second masking layer, and the third masking layer includes a second pattern over the first region and transferring the second pattern of the third masking layer to the second masking layer to form a third pattern from the second masking layer. The method further includes transferring the first pattern and the third pattern of the second masking layer to the first masking layer to form a fourth pattern and a fifth pattern from the first masking layer over the first region and the second region, respectively.