Abstract: A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage.

Abstract: A method of processing telephone voice output is used in an earphone. This method includes obtaining a corresponding adjustment parameter according to the phone identification information of the hearing-impaired so as to make the processing module in the earphone process the voice according to the adjustment parameter in advance and enable the hearing-impaired to hear more clearly.

Abstract: A method comprises identifying a number of power domains in a device, connecting the power domains to each other by a number of control devices during a wake-up mode of the device, and disconnecting the power domains after the wake-up mode of the device.

Abstract: Techniques are generally described related to tag refinement strategy. One example method for communicating between a first wireless system having a plurality of first antennas and a second wireless system having a plurality of second antennas may be presented. The method may include receiving configuration information associated with the plurality of first antennas and a plurality of modulation schemes which the first wireless system is configured to support; determining a plurality of configurations based on the configuration information, wherein each of the plurality of configurations defines a corresponding subset of first antennas selected from the plurality of first antennas and a corresponding modulation scheme selected from the plurality of modulation schemes; and selecting a first configuration from the plurality of configurations, wherein when operating under the first configuration, the first wireless system is configured to achieve one or more performance criteria.

Abstract: A checkpointing method for creating a file representing a restorable state of a virtual machine in a computing system, comprising identifying processes executing within the virtual machine that may store confidential data, and marking memory pages and files that potentially contain data stored by the identified processes; or providing an application programming interface for marking memory regions and files within the virtual machine that contain confidential data stored by processes; and creating a checkpoint file, by capturing memory pages and files representing a current state of the computing system, which excludes information from all of the marked memory pages and files.

Abstract: An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.

Abstract: A method of processing a sound segment is used in a hearing aid. If the sound segment is a high-frequency type, the high-frequency portion of the sound segment will be processed with a frequency lowering process. If the sound segment is a mixed-frequency type (between high-frequency and low-frequency), the energy of at least some portion of the high-frequency portion of the sound segment will be decreased and then processed with a frequency lowering process.

Abstract: An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract: A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

Abstract: Methods and apparatus for separating and removing aflatoxin-contaminated corn from batches of corn by a floating process, thus producing a distinguishable floating mat of contaminated corn and a separate submerged bed of uncontaminated and less contaminated corn. The methods of this disclosure include removing the floating contaminated corn mat by a vacuum mechanism or by liquid flow. The methods reduce the aflatoxin level in the submerged corn bed as much as 80% from the initial aflatoxin level, while removing no more than 15% from the batch of corn.

Abstract: A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.

Abstract: An axial flux Halbach rotor comprise: a first magnet set and a second magnet set. Further comprises: a plurality of first magnets that are respective featured by their respective first magnetizing directions and are arranged interconnecting to each other by the use of a first connecting element while allowing any two neighboring first magnets to be spaced from each other by a first distance; and the second magnet set further comprises: a plurality of second magnets that are respectively featured by their respective second magnetizing directions and are arranged interconnecting to each other by the use of a second connecting element while allowing any two neighboring second magnets to be spaced from each other by a second distance. In addition, the first magnet set and the second magnet set are arranged inlaid into each other while allowing the plural first magnets and the plural second magnets to be dispose alternatively.

Abstract: A wristband container for an earpiece is worn on a user's wrist. It is used for containing an earpiece. The wristband container for an earpiece includes a container main body, a first band, and a second band. The first band and the second band are connected to the container main body to form a circular space for the user's wrist. The first band and the second band are used to fix the wristband container for an earpiece on the user's wrist. The container main body has a containing space to contain an earpiece.

Abstract: A wound stator core disclosed is substantially formed from a spirally piled strip. In an embodiment, the strip with a specific length is formed with a first dentition and a second dentition, whereas the first dentition is featured by a first slot-number ratio and is composed of a first side and a plurality of first teeth in a manner that the plural first teeth are arranged as an array on the first side; which is also same to the second dentition while allowing the second slot-number ratio to be equal to the first slot-number ratio. In addition, each first tooth is formed with a first dental part at a free end thereof, while also each second tooth is formed with a second dental part at a free end thereof, and the first dental part of each first tooth is connected to the second dental part of its corresponding second tooth.

Abstract: A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

Abstract: A multimedia playing device includes a central processing unit, a plurality of sensors electrically coupled to the central processing unit, and an output unit electrically coupled to the central processing unit. The plurality of sensors are operated together with the central processing unit, such that after the sensors detect different hand movements of a user, the central processing unit reads and determines the hand movement and transmits related control signals to the output unit according to different hand movements to achieve the effects of using a hand posture to control related functional movements and enhancing the convenience of using the multimedia playing device.

Abstract: A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.

Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.

Abstract: A method of audio processing lowers the frequency of a high frequency audio area of an input audio in order to generate a lowered frequency audio area. The lowered frequency audio area is combined with the input audio to generate an output audio such that the output audio comprises the high frequency audio area, a low frequency audio area, and a lowered frequency audio area.