Abstract: A dual gate high electron mobility transistor (HEMT) includes a substrate, a channel layer above the substrate, a source electrode, a drain electrode, a first gate electrode, and a second gate electrode. The source electrode and the drain electrode are respectively electrically coupled to the channel layer and are respectively above the channel layer. The first gate electrode and the second gate electrode are respectively electrically coupled to the channel layer and are respectively above the channel layer. The first gate electrode is located between the source electrode and the drain electrode. The second gate electrode is located between the source electrode and the first gate electrode. The second gate electrode is biased with a DC voltage.

Abstract: A metal grid of a pixel array may be patterned with different sized openings over photodiodes. As a result, a uniform pixel array of photodiodes with different sensitivities may be formed. For example, the pixel array may include low-sensitivity photodiodes (LSPDs), mid-sensitivity photodiodes (MSPDs), and high-sensitivity photodiodes (HSPDs). The LSPDs, MSPDs, and HSPDs have different capture rates. Therefore, a higher dynamic range is achieved by combining signals from LSPDs, MSPDs, and HSPDs. For example, the pixel array may achieve a dynamic range of approximately 140 decibels or higher due to its increased capacity. Additionally, the pixel array exhibits better dark performance as compared to a pixel array with a combination of large photodiodes (LPDs) and small photodiodes (SPDs). Because each photodiode in the pixel array is approximately a same size, photodiode leakage is reduced as compared with irregular pixel arrays including a combination of LPDs and SPDs.

Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

Abstract: An electronic memory device includes a memory-cell circuit. The electronic memory device also includes a non-memory-cell circuit. The non-memory cell circuit includes an active region. The active region extends in a first direction in a top view. The active region includes a first segment and a second segment. The first segment has a first dimension measured in a second direction in the top view. The second segment has a second dimension measured in the second direction different from the first direction in the top view. The second dimension is different from the first dimension.

Abstract: The present invention discloses an intelligent ward round method and system based on an SSVEP electroencephalogram signal, the method including: the interactive terminal is used to present a visual stimulus source that includes a plurality of candidate intention options to the patient, the acquisition terminal is used to collect the patient's electroencephalogram signal, the electroencephalogram signal obtained by the acquisition terminal is transmitted to the interactive terminal for electroencephalogram signal recognition, the patient's expression intention is determined, and the expression intentions comprise disease intentions, privacy intentions, psychological intentions, physiological intentions, environmental intentions, and safety intentions, and the intelligent ward round is completed. This method greatly improving the ability of communication between the patient and medical staff.

Abstract: Examples described herein relate to processing packets. In some examples, based on receipt of a Hypertext Transfer Protocol (HTTP) packet at a network interface device, the HTTP packet comprising an HTTP body and HTTP header: provide the HTTP header, but not the HTTP body, for processing in user space; modify solely the HTTP header in user space; and in kernel space, combine the modified HTTP header and the HTTP body prior to transmission of the HTTP packet with modified HTTP header to a client.

Abstract: Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter.

Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a gate structure disposed on a substrate, source and drain regions, and first and second doped regions. The gate structure includes a gate disposed on the substrate, a gate dielectric layer disposed between the gate and the substrate, and a spacer disposed on sidewalls of the gate and the gate dielectric layer. The source and drain regions are disposed in the substrate and at two sides of the gate structure respectively. The first doped region is disposed in the substrate and adjacent to the source region. The second doped region is disposed in the substrate and located under the first doped region. The conductive type of the second doped region is opposite to that of the source region, the drain region and the first doped region.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

Abstract: The present disclosure relates to a field of hollow silica nanospheres. Particularly, the present disclosure relates to silica nanoparticles as adjuvant to induce or enhance immune response or as carrier to deliver antigen to a body.

Abstract: A two-stage speed controller includes a main body including a first port and a second port in communication with each other, and a primary channel and a secondary channel for fluid to flow therethrough. The secondary channel allows flowing in a single direction to a pressure accumulation chamber. A sliding-axle seat is arranged in the second port. An end of a sliding axle assembly forms, together with the sliding-axle seat, a valve. The pressure accumulation chamber is connected with a primary throttle channel. The sliding axle assembly is formed, in a transverse direction, with a secondary throttle channel. During ingress and discharging of the fluid, all the channels and movement of the valve together allow for control of the pressure of the fluid according to a magnitude of a spring force of a regulation assembly in order to control a moving speed of a cylinder connected to the main body.

Abstract: A facial beauty mask includes a light source part and a mask main body. The mask main body is connected to the light source part. The mask main body is provided with a first hollow part and a second hollow part. The first hollow part is used for exposing eyes, and the second hollow part is used for exposing a nose and a mouth. The mask main body is also provided with a breathable hollow part. The breathable hollow part, the first hollow part and the second hollow part are spaced apart from each other. Therefore, when a user uses the light emitted by the light source part to shine on the face for facial beauty, the first hollow part can be used for exposing the eyes, so that the user's eyes can observe the outside. The second hollow part can be used for exposing the nose and the mouth.

Abstract: A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6×D6.

Abstract: A seal including a seal material and a temperature control material in thermal communication with the seal material. A method for producing a seal having temperature regulating properties including adding a dopant to a seal material in a quantity that supports electrical conductivity and disposing an electrical connector on the seal. A borehole system comprising a borehole in a subsurface formation, a string in the borehole, and a seal tool disposed within or as a part of the string.

Abstract: Aspects herein are directed to a tensioning device for a strand on a knitting machine. The tensioning device includes a mounting plate that may be positioned between a strand source and a feeder bar. The mounting plate supports a first pulley, a second pulley and a weighted third pulley that is movable with respect to the first pulley and the second pulley. By routing a strand over the first pulley, under the third pulley and over the second pulley, additional tension may be added to the strand through the weight of the third pulley.

Abstract: Disclosed herein are methods of preparing composites from solid elastomer(s) and wet filler(s), as well as products, including composites, vulcanizates, and articles therefrom. The wet filler can have a liquid content of at least 15%. A resulting composite comprises the filler dispersed in the elastomer at a loading of at least 20 phr with a filler yield loss of no more than 10%, wherein the composite has a liquid content of no more than 10% by weight based on total weight of said composite.

Abstract: A memory system that is based on 3D NAND flash memory of a high capacity and/or capable of high performance is provided, which includes memory planes, each including a plane core and a specific set of resources. For each memory plane of the plurality of memory planes, the technology provides (i) a corresponding plane busy (PRDY) signal indicating a busy or a ready state of the specific set of recourses of the corresponding memory plane, and (ii) a corresponding plane in operation (PIO #) signal indicating an in operation or idle state of resources used by the plane core of the corresponding memory plane. Issuance of memory commands by a controller and execution of memory commands for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PIO # signals.

Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.