Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a dielectric layer, a conductive structure, a low-k dielectric layer and a plug. The conductive structure is disposed in the dielectric layer, having a recess portion. The low-k dielectric layer is disposed on the dielectric layer. The plug is disposed in the low-k dielectric layer and has a protruding bonding portion on the bottom of the plug. The bonding portion is extended into the dielectric layer and connected to the recess portion of the conductive structure.

Abstract: A die seal ring disposed in a die and surrounding an integrated circuit region of the die is described. The die seal ring has at least two different local widths.

Abstract: A bonding pad structure including a bonding pad and a passivation layer is described. The bonding pad is disposed on a chip. The passivation layer covers the bonding pad. In addition, the passivation layer has a first opening exposing a bonding region of the bonding pad and a second opening exposing a probing region of the bonding pad, respectively.

Abstract: A structure for preventing pad peeling includes a semiconductor substrate, a dielectric layer, a pad, and a protective layer. The semiconductor substrate has an active circuit structure. The dielectric layer is disposed on the semiconductor substrate and has an opening located in the dielectric layer above an edge position of the corresponding active circuit structure. Besides, the opening exposes a part of the surface of the active circuit structure. The pad disposed above the semiconductor substrate covers the dielectric layer above the position of the corresponding active circuit structure and fills up the opening. The protective layer is disposed on the dielectric layer and covers the edge of the pad.

Abstract: A method for fabricating a contact pad is disclosed. A first metal layer is disposed on a substrate for serving as a probing region. A second metal layer is disposed on the substrate thereafter to serve as an electrical connection region. Preferably, the first metal layer and the second metal layer are composed of different material and are electrically connected. The present invention uses two different metals to form a probing region and an electrical connection region of a contact pad. The probing region is used for providing a contacting surface for a test probe, whereas the electrical connection region is used for establishing an electrical connection in the later bumping or wire bonding process. By providing a contact pad having two different regions, the present invention is able to achieve probing process while prevent the surface of the contact pad from being damaged by the contact of test probes.

Abstract: First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer.

Abstract: A multi-chip package including a substrate, a first chip, a plurality of conductive bodies, a second chip, and a plurality of conductive studs is provided. The substrate has a first surface. The first chip disposed on the first surface has a first orthogonal projection on the first surface. The conductive bodies are disposed and electrically connected between the first chip and the first surface. The second chip disposed on the first surface has a second orthogonal projection on the first surface. At least part of the first chip is between the second chip and the substrate. The first orthogonal projection at least overlaps the second orthogonal projection. The conductive studs are disposed and electrically connected between the second chip and the first surface.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: An invention relating to an eFuse bar code structure and a method of using the bar code structure is disclosed. The bar code structure includes a substrate and a plurality of eFuse elements disposed on the substrate and arranged in a form of an array, such that a bar pattern can be formed by the result of whether the fuse of the eFuse elements is blown or not. The method of using the bar code structure includes, with respect to a data, fuses of the eFuse elements in the bar code structure being correspondingly blown in accordance with an encoding method to form a bar pattern. The eFuse bar code structure according to the present invention can be manufactured by using a semiconductor manufacturing process, and thus it has small volume, a high density and may record a huge number of data.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: A semiconductor wafer comprises a plurality of die areas, at least a first scribe line area and at least a second scribe line area surrounding each die area, at least a first metal structure positioned in the first scribe line area, and at least a second metal structure positioned in the second scribe line area. The first metal structure comprises at least a first slot split parallel to the first scribe line area, or comprises a plurality of openings arranged in an array. The second metal structure comprises at least a second slot split parallel to the second scribe line area, or comprises a plurality of openings arranged in an array.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

Abstract: A method of fabricating the structure for preventing the pad peeling is provided. A semiconductor substrate in which an active circuit structure has been formed is provided. Then, a dielectric layer with an opening is formed on the semiconductor substrate. The opening is formed in the dielectric layer above the edge position of the corresponding active circuit structure, and exposes a part of the surface of the active circuit structure. Then, a pad is formed above the semiconductor substrate to electrically connect the active circuit structure. The pad covers the dielectric layer above the position of the corresponding active circuit structure and fills up the opening. Then, a protective layer is formed to cover the surface of the dielectric layer and the edge of the pad.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

Abstract: A chip package structure including a substrate, a first chip and a second chip is provided. The first contacts and the second contacts of the substrate are respectively arranged to reside on a first side region and a second side region of the substrate. The first chip disposed on the substrate and has a plurality of first bonding pads arranged to reside on a first wire-bonding region of the first chip adjacent to the first contacts and are electrically connected to the first contacts via a plurality of first wires. The second chip is disposed on the first chip away from the symmetrical center of the first chip. The second chip has a plurality of second bonding pads arranged to reside on a second wire-bonding region of the second chip adjacent to the second contacts and are electrically connected to the second contacts via a plurality of second wires.

Abstract: A semiconductor package structure includes a semiconductor chip on which an electrical connection region having a plurality of chip bonding pads and a non-electrical connection region are defined, a substrate having a plurality of substrate bonding pads respectively corresponding to the chip bonding pads on a surface facing the semiconductor chip, a chip holder used for supporting the semiconductor chip, and a plurality of intermediate resilient conductive elements for electrically connecting the semiconductor chip to the substrate.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. WAT pads are disposed along the dicing line. Each of the WAT pads has thereon a slot opening. A reinforcement structure is formed within the slot opening and penetrates through the WAT pad for stopping propagation of de-lamination during wafer dicing.

Abstract: The invention is directed to an anti-fuse comprised of a substrate, a gate electrode, and a gate dielectric layer. The gate electrode is located on the substrate. The gate dielectric layer is placed between the gate electrode and the substrate. The method of programming the anti-fuse is accomplished by applying a bias voltage to between the gate electrode and the substrate to break down the gate dielectric layer and convert the resistance between the gate electrode and the substrate to be smaller than that before the breakdown of the gate dielectric layer happens. By using the anti-fuse, area occupied by the anti-fuse in the chip is decreased and the programming of the anti-fuse can be done after the chip is packed.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a substrate, a bond pad, a fuse structure and a protection layer. The substrate has a pad region and a fuse region. The bond pads are disposed in the pad region of the substrate. The fuse structure is disposed in the fuse region of the substrate. The protection layer is disposed on the substrate to cover the pad region and the fuse region so that the bond pads are prevented from oxidation.