Patents by Inventor Ping-Chuan Wang
Ping-Chuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153949Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.Type: ApplicationFiled: January 4, 2024Publication date: May 9, 2024Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
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Patent number: 11980016Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.Type: GrantFiled: July 20, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Chuan Yang, Chia-Hao Pao, Yu-Kuan Lin, Lien-Jung Hung, Ping-Wei Wang, Shih-Hao Lin
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Publication number: 20240103217Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.Type: ApplicationFiled: September 27, 2022Publication date: March 28, 2024Inventors: Brian McGowan, Ping-Chuan Wang, Oscar Restrepo
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Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
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Patent number: 10794948Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.Type: GrantFiled: November 7, 2017Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 10770407Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: GrantFiled: January 4, 2019Date of Patent: September 8, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, Jr., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Publication number: 20200219826Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, JR., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Patent number: 10677833Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.Type: GrantFiled: November 7, 2017Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 10388617Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.Type: GrantFiled: October 25, 2017Date of Patent: August 20, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Erdem Kaltalioglu, Ping-Chuan Wang, Ronald Gene Filippi, Jr.
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Patent number: 10325862Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.Type: GrantFiled: July 24, 2017Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Ronald G. Filippi, Erdem Kaltalioglu, Andrew T. Kim, Ping-Chuan Wang
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Patent number: 10304783Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.Type: GrantFiled: September 18, 2017Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: Erdem Kaltalioglu, Andrew T. Kim, Chengwen Pei, Ping-Chuan Wang
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Patent number: 10297546Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.Type: GrantFiled: July 18, 2017Date of Patent: May 21, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Erdem Kaltalioglu, Ronald G. Filippi, Jr., Ping-Chuan Wang, Cathryn Christiansen
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Publication number: 20190123005Abstract: The present disclosure relates generally to flip chip technology and more particularly, to a method for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure and a structure formed thereby. In an embodiment, a method is disclosed that includes forming a C4 pad on a patterned dielectric layer having grooves therein, the grooves providing an interfacial surface area between the patterned dielectric layer and the C4 pad sufficient to inhibit the C4 pad from delaminating during thermal expansion or contraction.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Erdem Kaltalioglu, Ping-Chuan Wang, Ronald Gene Filippi, JR.
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Patent number: 10229875Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: March 17, 2016Date of Patent: March 12, 2019Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 10199463Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: GrantFiled: February 27, 2018Date of Patent: February 5, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
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Publication number: 20190027433Abstract: Interconnect structures for a security application and methods of forming an interconnect structure for a security application. A sacrificial masking layer is formed that includes a plurality of particles arranged with a random distribution. An etch mask is formed using the sacrificial masking layer. A hardmask is etched while masked by the etch mask to define a plurality of mask features arranged with the random distribution. A dielectric layer is etched while masked by the hardmask to form a plurality of openings in the dielectric layer that are arranged at the locations of the mask features. The openings in the dielectric layer are filled with a conductor to define a plurality of conductive features.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Erdem Kaltalioglu, Ronald G. Filippi, JR., Ping-Chuan Wang, Cathryn Christiansen
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Publication number: 20180190770Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: ApplicationFiled: February 27, 2018Publication date: July 5, 2018Inventors: Waikin LI, Chengwen PEI, Ping-Chuan WANG
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Patent number: 9985615Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.Type: GrantFiled: February 1, 2017Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
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Patent number: 9966431Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.Type: GrantFiled: March 23, 2016Date of Patent: May 8, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Waikin Li, Chengwen Pei, Ping-Chuan Wang
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Patent number: 9960226Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.Type: GrantFiled: July 27, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Wai-Kin Li, Chengwen Pei, Ping-Chuan Wang