Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall.

Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: A semiconductor structure includes filled dual reinforcing trenches that reduce curvature of the semiconductor structure by stiffening the semiconductor structure. The filled dual reinforcing trenches reduce curvature by acting against transverse loading, axial loading, and/or torsional loading of the semiconductor structure that would otherwise result in semiconductor structure curvature. The filled dual reinforcing trenches may be located in an array throughout the semiconductor structure, in particular locations within the semiconductor structure, or at the perimeter of the semiconductor structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

Abstract: Structures that include isolation structures and methods for fabricating isolation structures. First and second trenches are etched in a substrate and surround a device region in which an integrated circuit is formed. A dielectric material is deposited in the first trench to define a first isolation structure, and an electrical conductor is deposited in the second trench to define a second isolation structure.

Abstract: Structures for a commonly-bodied field-effect transistors and methods of forming such structures. The structure includes a body of semiconductor material defined by a trench isolation region in a semiconductor substrate. The body includes a plurality of first sections, a plurality of second sections, and a third section, the second sections coupling the first sections and the third section. The third section includes a contact region used as a common-body contact for at least the first sections. The first sections and the third section have a first height and the second sections have a second height that is less than the first height.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical memory cell structures and methods of manufacture. The vertical memory cell includes a vertical nanowire capacitor and vertical pass gate transistor. The vertical nanowire capacitor composes of: a plurality of vertical nanowires extending from an insulator layer; a dielectric material on vertical sidewalls of the plurality of vertical nanowires; doped material provided between the plurality of vertical nanowire; the pass gate transistor composes of: high-k dielectric on top part of the nanowire, metal layer surrounding high-k material as all-around gate. And there is dielectric layer in between vertical nanowire capacitor and vertical nanowire transistor as insulator.

Abstract: A method, and forming an associated system, for testing semiconductor devices. Driver channels are provided, each driver channel connected to a storage device via a bus and connected to a respective semiconductor device. Each driver channel includes: a first voltage driver connected to the respective semiconductor device and having a first input for the respective semiconductor device, a second voltage driver connected to the respective semiconductor device and having a second input for the respective semiconductor device, first and second sets of optical switches in the first and second voltage driver respectively, and a microcontroller. All connections between the respective semiconductor device and both the first and second voltage drivers, in response to all optical switches of the first and second set of optical switches being closed. The semiconductor devices are tested, using the driver channels and the test parameters. The test results are provided to the storage device.

Abstract: A method for fabricating an interconnect function array includes forming a first plurality of conductive lines on a substrate, forming an insulator layer over the first plurality of conductive lines and the substrate, removing portions of the insulator layer to define cavities in the insulator layer that expose portions of the substrate and the first plurality of conductive lines, wherein the removal of the portions of the insulator layer results in a substantially random arrangement of cavities exposing portions of the substrate and the first plurality of conductive lines, depositing a conductive material in the cavities, and forming a second plurality of conductive lines on portions of the conductive material in the cavities and the insulator layer.

Abstract: Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.

Abstract: Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

Abstract: High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of capacitors in which each of the semiconductor nanorods serves as a bottom electrode for one of the plurality of capacitors, or a large-area metal-insulator-metal (MIM) capacitor in which the semiconductor nanorods serve as a support structure for a bottom electrode of the MIM capacitor subsequently formed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect reliability structures and methods of manufacture. The structure includes: a plurality of resistors; and a voltmeter configured to sense a relative difference in resistance of the plurality of resistors indicative of at least one of a via-depletion and line-depletion.

Abstract: A through-silicon-via (TSV) structure is formed within a trench located within a semiconductor structure. The TSV structure may include a first electrically conductive liner layer located on an outer surface of the trench and a first electrically conductive structure located on the first electrically conductive liner layer, whereby the first electrically conductive structure partially fills the trench. A second electrically conductive liner layer is located on the first electrically conductive structure, a dielectric layer is located on the second electrically conductive liner layer, while a third electrically conductive liner layer is located on the dielectric layer. A second electrically conductive structure is located on the third electrically conductive liner layer, whereby the second electrically conductive structure fills a remaining opening of the trench.

Abstract: A system, method and apparatus may comprise a wafer having a plurality of spiral test structures located on the kerf of the wafer. The spiral test structure may comprise a spiral connected at either end by a capacitor to allow the spiral test structure to resonate. The spiral structures may be located on a first metal layer or on multiple metal layers. The system may further incorporate a test apparatus having a frequency transmitter and a receiver. The test apparatus may be a sensing spiral which may be placed over the spiral test structures. A controller may provide a range of frequencies to the test apparatus and receiving the resonant frequencies from the test apparatus. The resonant frequencies will be seen as reductions in signal response at the test apparatus.