Abstract: The present disclosure discloses a blended ternary positive-electrode material, a preparation method thereof and a lithium ion battery, and relates to the field of lithium battery technologies. A temperature-sensitive precursor type material is taken as a raw material, a large-particle precursor, a small-particle precursor and lithium sources are presintered to obtain a first presintered material and a second presintered material, presintered materials and binders are then mixed, compacted and punctured to obtain a first to-be-sintered material block and a second to-be-sintered material block, the first to-be-sintered material block and the second to-be-sintered material block are loaded into a sagger together for primary sintering, and using a periphery-center regional mode or an upper-lower-layer distribution mode, the first presintered material is distributed at a periphery or an upper layer, and the second presintered material is distributed at a center or a lower layer.

Abstract: An electronic device may include a lenticular display. The lenticular display may have a lenticular lens film formed over an array of pixels. A plurality of lenticular lenses may extend across the length of the display. The lenticular lenses may be configured to enable stereoscopic viewing of the display such that a viewer perceives three-dimensional images. The display may have a number of independently controllable viewing zones. The viewer may be particularly susceptible to artifacts caused by crosstalk at the edge viewing zones within the primary field of view of the display. Certain types of content may also be more vulnerable to crosstalk than other types of content. Therefore, to mitigate crosstalk artifacts, the pixel value for each pixel may be adjusted based on the viewing zone of the respective pixel and content information (such as texture information or brightness information) associated with the respective pixel.

Abstract: An employee data replication system receives a request to replicate employee data hosted by a host system. At least one of: a live date corresponding to when the employee data is to be live on the enterprise system or a selection of one or more applications to be used on the enterprise system is identified. A cutoff date for the employee data is calculated based on one or more of the live date and the selection of one or more applications, the cutoff date indicating an oldest date for which the employee data is to be replicated to the enterprise system. Employee data is replicated from the host system to the enterprise system based on the cutoff date, and an indication is provided that the replication has completed.

Abstract: The dipole-resonator resistive absorber is a metamaterial absorber operating in the microwave regime. A single unit of the dipole-resonator resistive absorber includes a first rectangular conductive ring having a pair of first resistors mounted thereon and in electrical communication therewith, and a plurality of parallel linear arrays of second rectangular conductive rings, where each of the second rectangular conductive rings has a pair of second resistors mounted thereon and in electrical communication therewith. The first rectangular conductive ring is mounted above the plurality of parallel linear arrays of the second rectangular conductive rings, and this structure is backed by an electrically conductive layer. The single unit dipole-resonator resistive absorber may be expanded into an arrayed structure, forming a polarization-independent dipole-resonator resistive absorber.

Abstract: Methods and systems for budgeted and simplified training of deep neural networks (DNNs) are disclosed. In one example, a trainer is to train a DNN using a plurality of training sub-images derived from a down-sampled training image. A tester is to test the trained DNN using a plurality of testing sub-images derived from a down-sampled testing image. In another example, in a recurrent deep Q-network (RDQN) having a local attention mechanism located between a convolutional neural network (CNN) and a long-short time memory (LSTM), a plurality of feature maps are generated by the CNN from an input image. Hard-attention is applied by the local attention mechanism to the generated plurality of feature maps by selecting a subset of the generated feature maps. Soft attention is applied by the local attention mechanism to the selected subset of generated feature maps by providing weights to the selected subset of generated feature maps in obtaining weighted feature maps.

Abstract: Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.

Abstract: A semiconductor structure includes a semiconductor substrate, a metal gate structure disposed over the semiconductor substrate, an ILD structure over the semiconductor substrate and surrounding the metal gate structure, and a protecting layer over the ILD structure. A top surface of the protecting layer is aligned with a top surface of the metal gate structure. The protecting layer is separated from the metal gate structure.

Abstract: Disclosed herein are various embodiments for an employee data replication system. An embodiment operates by receiving a request to replicate employee data hosted by a host system. At least one of: a live date corresponding to when the employee data is to be live on the enterprise system or a selection of one or more applications to be used on the enterprise system is identified. A cutoff date for the employee data is calculated based on one or more of the live date and the selection of one or more applications, the cutoff date indicating an oldest date for which the employee data is to be replicated to the enterprise system. Employee data is replicated from the host system to the enterprise system based on the cutoff date, and an indication is provided that the replication has completed.

Abstract: A circuit board assembly includes a circuit board, a plurality of cables soldered to a side of the circuit board, a protective member covering a plurality of solder joints of the cables on the circuit board, and a retainer provided on the side of the circuit board. The retainer fixes the protective member on the circuit board.

Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: An accumulative repeat encoder facilitates encoding data written to memory, such that parity data is generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data is stored in memory. During a read operation, a decoder component utilizes the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component is iterative and provides one or more decoding results based on probabilities that symbols or bits comprising the data have correct values. The decoder component analyzes a decoding result and references a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result is determined to represent the original data and is provided as an output.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.

Abstract: Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

Abstract: Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Abstract: A LED system and driving device with error detection and an error detection module thereof is disclosed. In which, through the detection of the error detection module, the errors associated with the LED module and the driving circuit may be detected. If the errors are detected, the error detection module may output a determination signal to the control unit so that the LED system could be protected from damages.

Abstract: A lighting assembly is adapted to be connected to at least one conductive connection hole of an illumination device. The lighting assembly comprises at least one lighting cell and connection mechanism, wherein the lighting cell comprises a base, at least one electrical connector and a lighting unit. The electrical connector and the lighting unit are connected to the base, and electrically connected with each other. The lighting unit has a plurality of lighting circuits linearly arranged thereon, and one end of the connection mechanism is electrically connected to the electrical connector. When the lighting assembly only comprises one lighting cell, the other end of the connection mechanism is connected to the electrode connection hole; while when the lighting assembly comprises a plurality of said lighting cells, the other end of the connection mechanism is selectively connected to the conductive connection hole and the other electrical connector of the neighbor lighting cell.