Abstract: A device, system and method in which data in a write cache, that must at some point be written to non-volatile memory, is written to non-volatile memory after expiration of a threshold time period during which no new host commands are received. If either the last dirty entry is written back or a host command is received during the write-back process, the time threshold time period and auto-flush process is restarted.

Abstract: A superconducting article is provided that includes a substrate, an anti-epitaxial film over the substrate, a buffer film having biaxial crystal texture over the anti-epitaxial film, and a superconductor layer over the second buffer film. Also provided is a superconducting article as a tape, in a power cable, and a power transformer.

Abstract: Systems and methods for identifying error bits in encoded data are disclosed. As a part of identifying error bits, encoded data that is provided from a data source and that includes data and parity check portions is accessed. Based on the encoded data, syndromes are calculated, and based on the calculated syndromes, an equation is determined. The roots of the equation are determined and based on the determined roots of the equation, one or more error bits are identified. The error bits are identified using a circuit that presents a binary representation of the roots. The error bits are corrected based on the error bits that are identified.

Abstract: Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

Abstract: Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory.

Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.

Abstract: Systems and methods for improving the performance and reliability of flash memory solid state drive devices are described herein. A flash memory array component stores data. A memory hierarchy component transfers data between the host and the flash memory array component. The memory hierarchy component includes a level one (“L1”) cache coupled to a merge buffer, the flash memory array component, and the host. The merge buffer is coupled to the flash memory array component. The L1 cache and merge buffer include volatile memory, and the host is coupled to the merge buffer and flash memory array component. The memory hierarchy component includes a write component and a read component. The write component writes data to at least one of the L1 cache, merge buffer, or flash memory array component. The read component reads data from at least one of the L1 cache, merge buffer, or flash memory array component.

Abstract: Systems and/or methods that provide for the accuracy of address translations in a memory system that decouples the system address from the physical address. Address-modifying transactions are recorded in a non-volatile write buffer to couple the last-in-time translation physical address/location with the current translated physical location/address. In addition, integrity check protection may be applied to the translation and to the written data to limit the amount of data that may be lost in the event of a failure/error occurring during the write operation. Transaction recording and integrity check protection allows for recovery of write operations that may not have fully completed due to the failure/error.

Abstract: An illumination assembly comprises a base and at least one illumination cell. The base comprises a supply circuit for supplying an external power after connecting to a power source. The illumination cell is optionally connected to the base or removed from thereof, and includes a power storage unit stored with a storage power, a discharging circuit, and a charging circuit, wherein the power storage unit is electrically connected to the discharging circuit and the charging circuit. When the illumination cell is removed from the base, the storage power released from the power storage unit drives the illumination cell projecting an illumination light beam via the discharging circuit. When the illumination cell is assembled to the base, the supply circuit is electrically connected to the discharging circuit and the charging circuit respectively, so that the external power can drive the illumination cell projecting the illumination light beam and charge the power storage unit simultaneously.

Abstract: An accumulative repeat encoder can facilitate encoding data written to memory, such that parity data can be generated in accordance with a low-density parity-check (LDPC) code. The original data and associated parity data can be stored in memory. During a read operation, a decoder component can utilize the parity data based on the LDPC code to facilitate decoding the data being read from memory. The decoder component can be iterative and can provide one or more decoding results based on certain probability calculations as to the values of the read data. The decoder component can analyze a decoding result and reference a parity-check matrix structured in accordance with the LDPC code to determine the accuracy of the decoding result. If the decoding result attains a desired accuracy, the decoding result can be representation of the original data and can be provided as an output.

Abstract: A lighting assembly is adapted to be connected to at least one conductive connection hole of an illumination device. The lighting assembly comprises at least one lighting cell and connection mechanism, wherein the lighting cell comprises a base, at least one electrical connector and a lighting unit. The electrical connector and the lighting unit are connected to the base, and electrically connected with each other. The lighting unit has a plurality of lighting circuits linearly arranged thereon, and one end of the connection mechanism is electrically connected to the electrical connector. When the lighting assembly only comprises one lighting cell, the other end of the connection mechanism is connected to the electrode connection hole; while when the lighting assembly comprises a plurality of said lighting cells, the other end of the connection mechanism is selectively connected to the conductive connection hole and the other electrical connector of the neighbor lighting cell.

Abstract: A superconducting article and a method of making a superconducting article is described. The method of forming a superconducting article includes providing a substrate, forming a buffer layer to overlie the substrate, the buffer layer including a first buffer film deposited in the presence of an ion beam assist source and having a uniaxial crystal texture. The method further includes forming a superconducting layer to overlie the buffer layer.

Abstract: Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.

Abstract: An illumination assembly comprises a base and at least one illumination cell. The base comprises a supply circuit for supplying an external power after connecting to a power source. The illumination cell is optionally connected to the base or removed from thereof, and includes a power storage unit stored with a storage power, a discharging circuit, and a charging circuit, wherein the power storage unit is electrically connected to the discharging circuit and the charging circuit. When the illumination cell is removed from the base, the storage power released from the power storage unit drives the illumination cell projecting an illumination light beam via the discharging circuit. When the illumination cell is assembled to the base, the supply circuit is electrically connected to the discharging circuit and the charging circuit respectively, so that the external power can drive the illumination cell projecting the illumination light beam and charge the power storage unit simultaneously.

Abstract: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.

Abstract: A channel tracking module, configured for generating updated equalization coefficients for a frequency equalizer, is configured for determining a digital-based error value between equalized signals output by the frequency equalizer relative to predicted signals, for each subcarrier frequency of an OFDM symbol. The channel tracking module determines an accumulated error based on accumulating the digital-based error values for all the subcarrier frequencies of the OFDM symbol, for a prescribed successive number of OFDM symbols. The channel tracking module also determines a step size based on the accumulated error and relative to a prescribed step function configured for optimizing equalizer adjustments within stability limits. The channel tracking updates the equalization coefficients for each subscarrier frequency based on the accumulated error and the step size.

Abstract: A channel estimator is configured for determining a gain adjustment for a received wireless signal having a prescribed plurality of tones. The channel estimator is configured for generating, for each of the tones, a corresponding pseudo power value representing a detected power level for the corresponding tone. An accumulated pseudo power value is obtained based on accumulating the respective pseudo power values of the prescribed plurality of tones. Each of the pseudo power values is selectively adjusted by an adjustment factor based on a determined difference between the accumulated pseudo power value relative to an expected accumulated power level relative to a prescribed dynamic range. The pseudo power values are then output for decoding of data modulated at the respective tones.

Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.