Abstract: A method for molding a composite component, which includes step (a) of providing a forming mold and a preformed substrate, in which the forming mold includes a lower mold and an upper mold matched with each other; step (b) of disposing the preformed substrate into an accommodating space, and clamping the upper mold against the lower mold such that a mold cavity is formed between the preformed substrate and the upper mold; step (c) of injecting a polymer material into the mold cavity from a sprue of the upper mold under an injecting pressure, while pushing the preformed substrate by the polymer material which is formed by the injecting pressure, thereby forming a first deformed portion; and step (d) of further clamping the upper mold against the lower mold using a molding pressure, while pushing the polymer material and the first deformed portion, thereby obtaining a semi-finished product.

Abstract: A touch module includes a base plate, a first magnet, a second magnet, a touch pad, a first magnetic board and a second magnetic board. The first magnet and the second magnet are installed on the base plate and separated from each other. The touch pad is located over the base plate to cover the first magnet and the second magnet. The first magnetic board and the second magnetic board are separated from each other, located under the touch pad and coupled with the touch pad. The first magnetic board is aligned with the first magnet. The second magnetic board is aligned with the second magnet. The driving circuit is electrically coupled with the first magnetic board and the second magnetic board. The first magnetic board induces a magnetic field of the first magnet. The second magnetic board induces a magnetic field of the second magnet.

Abstract: A feedback loop circuit of a voltage regulator includes a loadline and a compensation circuit. The loadline generates a feedback signal according to a sensed current signal that provides information of an inductor current of the voltage regulator, and outputs the feedback signal to a controller circuit of the voltage regulator for regulating an output voltage of the voltage regulator. The compensation circuit generates a compensation signal to compensate for a deviation of the output voltage, wherein the feedback signal generated from the loadline is affected by the compensation signal.

Abstract: A method for manufacturing a composite structure having first and second structural members includes the steps of: (A) placing a plate in a forming mold having a first molding member, and a second molding member with an injection hole; (B) moving the first molding member toward the second molding member to stamp and deform the plate; (C) injecting a molten substrate onto the plate via the injection hole to stamp and deform again the plate so as to form the first structural member; (D) removing an assembly of the first structural member and a solidified substrate from the first molding member; and (E) removing an excess part of the solidified substrate to form the second structural member.

Abstract: The embodiments of the present invention provide a user equipment positioning method, apparatus, a base station and a storage medium, and relates to the technical field of wireless communication.

Abstract: A circuit board includes a plurality of pixel areas. Each pixel area includes a plurality of electrode pad groups. The electrode pad groups are arranged in a first direction. Each of the electrode pad groups includes a first electrode pad, a second electrode pad, and a third electrode pad. The first electrode pad, the second electrode pad, and the third electrode pad are arranged in a second direction. The second direction is different from the first direction. The first electrode pad is disposed between the second electrode pad and the third electrode pad. The first electrode pad is configured to provide a first voltage potential. The second electrode pad and the third electrode pad are configured to provide a second voltage potential. The first voltage potential is different from the second voltage potential.

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

Abstract: A barrier panel is formed of a first rail member and a second rail member with at least one vertical support member mounted to and extending between the first rail member and second rail member. The first rail member includes first openings spaced apart along its length. The second rail member includes second openings spaced apart along its length. Vertical cables are mounted to and extend between the first rail member and second rail member. A first end of each vertical cable is secured within one of the first openings and a second end of each vertical cable is secured within an opposite one of the second openings. End members configured to adjust tension in the vertical cables are concealed by a pair of leg members of the second rail member.

Abstract: A lighting apparatus includes a light source module, a driver and a processor. The light source module includes multiple light zones. Different light zones have different LED module combinations. The driver is coupled to an external power source to generating driving currents to the light source module. The processor receives a control command for adjusting colors of the multiple light zones separately by sending control signals to the driver. The control signals indicate duty ratios of the multiple LED modules of the multiple light zones to adjust the colors of the multiple light zones.

Abstract: The present disclosure provides a memory device and the forming method thereof. The memory device includes a gate structure on a substrate, a source/drain region in a substrate, a dielectric layer covering the substrate and the gate structure, and a cell contact adjacent to the gate structure. The cell contact includes a conductive layer, a first barrier layer on a sidewall of the conductive layer, and a second barrier layer on a bottom surface of the conductive layer. The second barrier layer directly contacts the first barrier layer and the source/drain region. A second resistivity of the second barrier layer is lower than a first resistivity of the first barrier layer.

Abstract: A method of tuning parameters for image signal processing is provided. The method includes capturing at least one raw image. The method further includes generating a first rendered image by rendering the raw image based on a first parameter value set, and generating a second rendered image by rendering the raw image based on a second parameter value set. The method further includes calculating a first image quality score set for the first rendered image, and calculating a second image quality score set for the second rendered image. The method further includes generating a third parameter value set based on the first parameter value set, the second parameter value set, the first image quality score set, and the second image quality score set.

Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.

Abstract: A two-component adhesive composition comprising the reaction product of: a polyol component, comprising at least one hydrophobic polyol: and an isocyanate component, comprising polyphosphoric acid and the reaction product of (I) an isocyanate compound and (II) a dimer acid polyester polyol.

Abstract: A power divider network includes a cover plate, a reflection plate, a support component, and a feed line. The reflection plate is arranged separately from the cover plate. A first surface of the reflection plate is a reflection surface. A plurality of connectors protrude from a second surface of the reflection plate opposite to the reflection surface. The plurality of connectors are arranged at intervals. The plurality of connectors are coupled with the cover plate and divide the space between the reflection plate and the cover plate into at least one hollow chamber. The support component is at least partially arranged in the hollow chamber. The feed line is arranged in the hollow chamber and mounted at the support component.

Abstract: A method of using a coupling system includes aligning an optical fiber with a cavity in a chip, wherein aligning the optical fiber comprises orienting the fiber within an angle ranging from about 88-degrees to about 92-degrees with respect to a top surface of the chip. The method further includes emitting an optical signal from the optical fiber. The method further includes redirecting the optical signal into a waveguide using a grating positioned on an opposite side of the cavity from the optical fiber.

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride layer is thicker than the first nitride layer.

Abstract: The present disclosure provides an electronic device, and the electronic device includes a first substrate, a first circuit layer, a touch sensing element, a touch sensing circuit, a bio-feature sensing element, a second substrate, a second circuit layer, a bio-feature sensing circuit, a plurality of pixels and a blocking layer. The touch sensing element overlaps with the first substrate and includes a plurality of touch sensing electrodes. The touch sensing circuit is coupled to the touch sensing element through the first circuit layer. The second circuit layer is overlapped with the second substrate. The bio-feature sensing circuit is coupled to the bio-feature sensing element through the second circuit layer, wherein a distance between the second side edge of the second substrate and the bio-feature sensing circuit is less than a distance between the first side edge of the substrate and the touch sensing circuit.

Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1A), a second access transistor (PG1B), a third access transistor (PG2A) and a fourth access transistor (PG2B). A first word line contact pad connected to a gate of the first access transistor (PG1A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG1B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.