Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A hemming path planning method and a hemming system are provided. The hemming path planning method includes the following steps. An initial contour data of a target is scanned to obtain. A first segment of the hemming path is planned according to the initial contour data. The first segment corresponds to a first bending angle. A second segment of the hemming path is planned according to the initial contour data and an expected springback amount related to the first bending angle. The second segment corresponds to a second bending angle. The first segment and the second segment are combined to obtain a continuous hemming path.

Abstract: A transistor structure includes a substrate, an isolation wall, and a gate region. The substrate has a fin structure. The isolation wall clamps sidewalls of the fin structure. The gate region is above the fin structure and the isolation wall; wherein the isolation wall is configured to prevent the fin structure from collapsing.

Abstract: A fan engagement structure for the fan to quickly and securely plug into or extract out of another structure. The fan engagement structure includes a frame main body. The frame main body has a first end and a second end. The frame main body has an internal hollow passage. The first end is mated with a fan. The frame main body has a first side and a second side. An engagement elastic plate extends from the first side. The surface of the engagement elastic plate has a latch section. The second side has a finger latch section, whereby the fan can be quickly and securely plugged into or extracted out of the other structure.

Abstract: The present disclosure provides an optical waveguide connection assembly and an optical module including the optical waveguide connection assembly. The optical waveguide connection assembly includes a holder, an optical fiber, a connection member and an optical coefficient adjusting member. The holder has a first part and a second part. The first part is positioned a side of the optical element, the second part is positioned above the optical element. The optical fiber is fixed to the first par. The connection member is provided between the second part and the optical element. The optical coefficient adjusting member is provided between the optical fiber and the optical element, so that a beam is capable of being transferred between the optical fiber and the optical element via the optical coefficient adjusting member. The optical waveguide connection assembly is fixed to the optical element via the connection member and the optical coefficient adjusting member.

Abstract: The invention provides a heat treatment method for a steel product. The steel product includes at least 0.5-0.7% of Si by weight; the method provides the following steps: step 1) putting the steel product under an Austenitizing temperature of 830-890° C. and lasting for a first time to Austenitize the steel product, step 2) immersing the Austenitized steel product in a salt bath at an isothermal temperature of 200-350° C. and lasting for the second time. The method of the invention improves the toughness and elongation of the steel product, keeps the wear resistance of the product, and can be well applied to the fields of thin section ring of bearings and the like. The invention also provides a steel product and a bearing ring.

Abstract: A vertical cable barrier includes a top rail defining a plurality of top through holes spaced apart along a top web portion. A bottom rail includes a bottom web portion and a pair of bottom leg portions, where the bottom web portion and the pair of bottom leg portions form a channel, and the bottom web portion defines a plurality of bottom through holes spaced apart along the bottom web portion and aligned with the top through holes. A vertical cable is disposed on each side of a rigid support member. Each vertical cable includes a top end directly attached to a hollow tubular shank of a first top swage fitting and a bottom end of received in and directly attached to a hollow tubular shank of a first bottom swage fitting, where the top end of the vertical cable extends through one of the plurality of top through holes, and the bottom end of the vertical cable extends through one of the bottom through holes that is disposed in vertical alignment with the one top through hole.

Abstract: An antenna device includes a differential-line, a first metal and a second metal. The differential-line includes a first line and a second line. The first metal and second metal are coupled to the first line and second line respectively. The first metal and second metal have different shapes and/or different sizes. The first metal and second metal form symmetric or asymmetric dipole. The first metal and second metal can be disposed on the same plane or different planes, can be electrically insulated and can have a first slot and a second slot respectively. The antenna device can further include a base coupled to the first line and second line. The base can be a daughter board having a front-end module or not. The IC package in daughter board can have different sizes. The daughter board can be offset by different distances and can be coupled to a mother board.

Abstract: A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (?) is the same or substantially the same.

Abstract: A power module of an electric assisted bicycle is disclosed and includes a pedal shaft, a gear-plate-output shaft, a reducer-output shaft and a motor-output shaft. The pedal shaft is arranged along an axial direction. The gear-plate-output shaft includes a first section and a second section arranged in the axial direction. The first section is concentrically sleeved on the pedal shaft through a first one-way bearing along a radial direction. When the pedal shaft is forced to rotate, the gear-plate-output shaft is driven through the first one-way bearing. The reducer-output shaft is concentrically sleeved on an outer surface of the second section through a second one-way bearing along the radial direction. The motor-output shaft is concentrically sleeved on the reducer-output shaft along the radial direction. When the motor-output shaft drives the reducer-output shaft to rotate, the gear-plate-output shaft is driven by the reducer-output shaft through the second one-way bearing.

Abstract: A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.

Abstract: A standard cell includes a plurality of transistors, a set of contacts coupled to the plurality of transistors, at least one input line electrically coupled to the plurality of transistors, an output line electrically coupled to the plurality of transistors, a VDD contacting line electrically coupled to the plurality of transistors and a VSS contacting line electrically coupled to the plurality of transistors. Wherein as a minimum feature size (?) of the standard cell gradually decreases from 22 nm, an area size of the standard cell in terms of ?2 is the same or substantially the same.

Abstract: Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

Abstract: An electronic device includes a substrate including an active area and a peripheral area adjacent to the active area; a plurality of spacers disposed in the active area and including a first spacer and a second spacer; a plurality of signal lines disposed on the substrate and extending along a first direction; a plurality of gate lines disposed on the substrate and extending along a second direction; and a gate driving unit disposed in the active area and including a receiving switch element and a buffer switch element, wherein the receiving switch element is disposed corresponding to the first spacer and receives an input signal through one of the signal lines, and the buffer switch element is disposed corresponding to the second spacer and is electrically connected to the receiving switch element, wherein the buffer switch element outputs a scan signal to one of the gate lines.

Abstract: An optical module includes a waveguide interposer and at least one light source unit. The waveguide interposer includes at least one input terminal, at least one waveguide channel, and at least one output terminal. The at least one input terminal is configured to receive laser light, and the at least one waveguide channel is coupled to the at least one input terminal and is configured to guide the laser light. Each light source unit is configured to output the laser light to a corresponding input terminal of the at least one input terminal.

Abstract: A method for forming a transistor structure includes steps as follows: A substrate with an original surface is prepared. Next a gate conductive region is formed, wherein at least a portion of the gate conductive region is disposed below the original surface, and a bottom wall and sidewalls of the gate conductive region is surrounded by a gate dielectric layer. Then, a first conductive region is formed, wherein a bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: A transistor structure includes a substrate, a gate conductive region, a gate dielectric layer and a first conductive region. At least a portion of the gate conductive region is disposed below a surface of the substrate. The gate dielectric layer surrounds a bottom wall and sidewalls of the gate conductive region. A bottom wall of the first conductive region is aligned or substantially aligned with a top wall of the gate conductive region.

Abstract: A braiding path generating method includes the following steps. Firstly, a mandrel model is received. Then, an outer diameter of the mandrel model is obtained. Then, a target braiding angle is obtained according to a target coverage rate and the outer diameter of the mandrel model. Then, a braiding simulation path is generated according to the target braiding angle.

Abstract: A targeted temperature management (TTM) system is disclosed that includes a TTM module to provide a TTM fluid, a fluid delivery line (FDL) including a FDL hub, a fluid delivery lumen and a fluid return lumen, and a pad to facilitate thermal energy transfer between the TTM fluid and a patient, the pad including a fluid delivery conduit extending away from the pad portion and including a first leak prevention valve configured to enable the TTM fluid to flow in a distal direction while preventing flow in a proximal direction, and a fluid return conduit extending away from the pad portion, the fluid return conduit including (i) a return conduit connector at a proximal end thereof, and (ii) a second leak prevention valve configured to enable the TTM fluid to flow in the proximal direction while preventing flow in the distal direction.