Patents by Inventor Ping Kao
Ping Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240162602Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.Type: ApplicationFiled: January 2, 2024Publication date: May 16, 2024Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN
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Patent number: 11979614Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.Type: GrantFiled: July 2, 2021Date of Patent: May 7, 2024Assignee: INTERDIGITAL VC HOLDINGS, INC.Inventors: Meng-Ping Kao, Peng Yin, Oscar Divorra Escoda
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Publication number: 20240126327Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.Type: ApplicationFiled: October 14, 2022Publication date: April 18, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
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Publication number: 20240117342Abstract: An construction method of an embryonic chromosome signal library is provided. The construction method comprises obtaining an embryo and performing whole-genome amplification and next-generation sequencing to obtain a first chromosome signal; mapping the first chromosome signal to a chromosome reference signal to obtain a second chromosome signal; dividing the second chromosome signal within a predetermined interval range to obtain a third chromosome signal; and performing a regression correction on the sequencing read count (RC) of the third chromosome signal to obtain an embryonic chromosome signal library. Furthermore, a detection method and system of embryonic chromosomes are also provided. Thereby, the information comparison of the embryo chromosome signal library is used to determine whether the pre-implantation embryo is abnormal or not to achieve pre-implantation chromosome screening of pre-implantation embryos.Type: ApplicationFiled: October 2, 2023Publication date: April 11, 2024Inventors: LI-JEN SU, SHAO-PING WENG, YU-YU YEN, LI-CHING WU, HUI-YIN CHIU, JUI-HUNG KAO
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Patent number: 11942363Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.Type: GrantFiled: August 9, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Kuei-Yu Kao, Chen-Ping Chen, Chih-Han Lin
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Publication number: 20240096705Abstract: A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuei-Yu Kao, Chen-Yui Yang, Hsien-Chung Huang, Chao-Cheng Chen, Shih-Yao Lin, Chih-Chung Chiu, Chih-Han Lin, Chen-Ping Chen, Ke-Chia Tseng, Ming-Ching Chang
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11923440Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.Type: GrantFiled: July 26, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chen-Ping Chen, Kuei-Yu Kao, Hsiao Wen Lee, Chih-Han Lin
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Patent number: 11912827Abstract: A poly(imide-ester-amide) copolymer and an optical film are provided. The poly(imide-ester-amide) copolymer includes imide bonds, ester bonds, and amide bonds. A molar ratio of the imide bonds, the ester bonds, and the amide bonds is 40 to 80:10 to 30:5 to 30. The imide bonds are derived from an aromatic diamine monomer and a tetracarboxylic dianhydride monomer. The amide bonds are derived from an aromatic dicarboxylic acid dichloride monomer and an aromatic diamine monomer or is derived from the aromatic dicarboxylic acid dichloride monomer and an alkoxysilane containing an amine group or an isocyanate group.Type: GrantFiled: February 5, 2020Date of Patent: February 27, 2024Assignee: Daxin Materials CorporationInventors: Guan-Ping Chen, Min-Tzu Kao
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Patent number: 11644427Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.Type: GrantFiled: November 23, 2020Date of Patent: May 9, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Feng Hsiao, Chung-Hsuan Wu, Shuo-Yu Chen, Nai-Ying Lo, Yi-Hui Tseng, Chen-Hui Huang, Yung-Yu Yang, Tzu-Ping Kao
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Publication number: 20220128485Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.Type: ApplicationFiled: November 23, 2020Publication date: April 28, 2022Inventors: Chia-Feng HSIAO, Chung-Hsuan WU, Shuo-Yu CHEN, Nai-Ying LO, Yi-Hui TSENG, Chen-Hui HUANG, Yung-Yu YANG, Tzu-Ping KAO
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Patent number: 11298579Abstract: A resistance supplier for weight training has two switching assemblies, two planetary gear sets, a one-way output bearing, a spindle, and at least one weight. The two switching assemblies respectively control input, output, and fixing of the sun gear, planet carrier, and ring gear in the two planetary gear sets. The output of one of the two planetary gear sets is used as the input of the other planetary gear set. Therefore, the two planetary gear sets provide three reduction ratios and transmit torque to the spindle through the one-way output bearing to drive the weight to rotate. By using reduction ratios of the planetary gear sets to increase the output requirement of the user and switching gears via switching assemblies to change reduction ratios, the resistance supplier can provide sufficient and diverse training resistances with a single weight, thereby reducing the volume.Type: GrantFiled: August 26, 2020Date of Patent: April 12, 2022Inventor: Chien-Ping Kao
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Publication number: 20220062691Abstract: A resistance supplier for weight training has two switching assemblies, two planetary gear sets, a one-way output bearing, a spindle, and at least one weight. The two switching assemblies respectively control input, output, and fixing of the sun gear, planet carrier, and ring gear in the two planetary gear sets. The output of one of the two planetary gear sets is used as the input of the other planetary gear set. Therefore, the two planetary gear sets provide three reduction ratios and transmit torque to the spindle through the one-way output bearing to drive the weight to rotate. By using reduction ratios of the planetary gear sets to increase the output requirement of the user and switching gears via switching assemblies to change reduction ratios, the resistance supplier can provide sufficient and diverse training resistances with a single weight, thereby reducing the volume.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Inventor: Chien-Ping KAO
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Patent number: 11233348Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.Type: GrantFiled: April 24, 2020Date of Patent: January 25, 2022Assignee: Intel CorporationInventors: Se-Jung Moon, Chien-Ping Kao, Gaudencio Hernandez Sosa, Beom-Taek Lee
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Publication number: 20210337241Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: MENG-PING KAO, PENG YIN, OSCAR DIVORRA ESCODA
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Patent number: 11151724Abstract: An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.Type: GrantFiled: June 3, 2019Date of Patent: October 19, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tzu-Ping Kao, Ching-Hsing Hsieh, Chia-Chi Chang, Ju-Te Chen, Chen-Hui Huang, Cheng-Hsien Chen
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Patent number: 11089337Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.Type: GrantFiled: May 3, 2017Date of Patent: August 10, 2021Assignee: INTERDIGITAL VC HOLDINGS, INC.Inventors: Meng-Ping Kao, Peng Yin, Oscar Divorra Escoda
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Publication number: 20210159625Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.Type: ApplicationFiled: April 24, 2020Publication date: May 27, 2021Inventors: Se-Jung MOON, Chien-Ping KAO, Gaudencio HERNANDEZ SOSA, Beom-Taek LEE
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Publication number: 20200380693Abstract: An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.Type: ApplicationFiled: June 3, 2019Publication date: December 3, 2020Inventors: Tzu-Ping KAO, Ching-Hsing HSIEH, Chia-Chi CHANG, Ju-Te CHEN, Chen-Hui HUANG, Cheng-Hsien CHEN
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Patent number: 10114437Abstract: A portable device is provided. A first processor performs an initial procedure according to an operation clock with a first frequency value and an operation voltage with a first voltage value, and performs a calibration procedure according to the operation clock with a second frequency value and the operation voltage with a second voltage value when the initial procedure has been performed and a self-calibration event is present. A second processor detects whether a specific function of the calibration procedure is being performed by the first processor. The second processor stores the second frequency value and the second voltage value into a storage unit after the calibration procedure is performed. The second voltage value is lower than the first voltage value, and the second frequency value is lower than the first frequency value.Type: GrantFiled: July 28, 2016Date of Patent: October 30, 2018Assignee: MEDIATEK INC.Inventors: Yi-Chang Zhuang, Lee-Kee Yong, Wu-an Kuo, Yi-Ping Kao, Alice Wang, Uming Ko