Patents by Inventor Ping Kao

Ping Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151262
    Abstract: A microelectronic device includes a semiconductor base structure, word lines, digit line contacts, digit lines, and storage node contacts. The semiconductor base structure includes pillar structures horizontally separated from one another by filled isolation trenches. The word lines horizontally extend through the pillar structures and the filled isolation trenches in a first direction. The digit line contacts include conductively doped semiconductor material vertically extending into digit line contact sections of the pillar structures. The digit lines are over and in contact with the digit line contacts and horizontally extend in a second direction orthogonal to the first direction. The digit lines have a different material composition than the digit line contacts. The storage node contacts include additional conductively doped semiconductor material vertically extending into storage node contact sections of the pillar structures. Methods, memory devices, and electronic systems are also described.
    Type: Application
    Filed: October 3, 2024
    Publication date: May 8, 2025
    Inventors: Ping Kao, Soichi Sugiura, Yoshihiro Matsumoto, Cheng En Lue
  • Publication number: 20240244270
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Application
    Filed: April 1, 2024
    Publication date: July 18, 2024
    Inventors: MENG-PING KAO, PENG YIN, OSCAR DIVORRA ESCODA
  • Patent number: 11979614
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: May 7, 2024
    Assignee: INTERDIGITAL VC HOLDINGS, INC.
    Inventors: Meng-Ping Kao, Peng Yin, Oscar Divorra Escoda
  • Patent number: 11644427
    Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 9, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Feng Hsiao, Chung-Hsuan Wu, Shuo-Yu Chen, Nai-Ying Lo, Yi-Hui Tseng, Chen-Hui Huang, Yung-Yu Yang, Tzu-Ping Kao
  • Publication number: 20220128485
    Abstract: An automatic detection method and an automatic detection system for detecting any crack on wafer edges are provided. The automatic detection method includes the following steps. Several wafer images of several wafers are obtained. The wafer images are integrated to create a templet image. Each of the wafer images is compared with the templet image to obtain a differential image. Each of the differential images is binarized. Each of the differential images which are binarized is de-noised. Whether each of the differential images has an edge crack is detected according to pattern of each of the differential images which are de-noised.
    Type: Application
    Filed: November 23, 2020
    Publication date: April 28, 2022
    Inventors: Chia-Feng HSIAO, Chung-Hsuan WU, Shuo-Yu CHEN, Nai-Ying LO, Yi-Hui TSENG, Chen-Hui HUANG, Yung-Yu YANG, Tzu-Ping KAO
  • Patent number: 11298579
    Abstract: A resistance supplier for weight training has two switching assemblies, two planetary gear sets, a one-way output bearing, a spindle, and at least one weight. The two switching assemblies respectively control input, output, and fixing of the sun gear, planet carrier, and ring gear in the two planetary gear sets. The output of one of the two planetary gear sets is used as the input of the other planetary gear set. Therefore, the two planetary gear sets provide three reduction ratios and transmit torque to the spindle through the one-way output bearing to drive the weight to rotate. By using reduction ratios of the planetary gear sets to increase the output requirement of the user and switching gears via switching assemblies to change reduction ratios, the resistance supplier can provide sufficient and diverse training resistances with a single weight, thereby reducing the volume.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 12, 2022
    Inventor: Chien-Ping Kao
  • Publication number: 20220062691
    Abstract: A resistance supplier for weight training has two switching assemblies, two planetary gear sets, a one-way output bearing, a spindle, and at least one weight. The two switching assemblies respectively control input, output, and fixing of the sun gear, planet carrier, and ring gear in the two planetary gear sets. The output of one of the two planetary gear sets is used as the input of the other planetary gear set. Therefore, the two planetary gear sets provide three reduction ratios and transmit torque to the spindle through the one-way output bearing to drive the weight to rotate. By using reduction ratios of the planetary gear sets to increase the output requirement of the user and switching gears via switching assemblies to change reduction ratios, the resistance supplier can provide sufficient and diverse training resistances with a single weight, thereby reducing the volume.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 3, 2022
    Inventor: Chien-Ping KAO
  • Patent number: 11233348
    Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: January 25, 2022
    Assignee: Intel Corporation
    Inventors: Se-Jung Moon, Chien-Ping Kao, Gaudencio Hernandez Sosa, Beom-Taek Lee
  • Publication number: 20210337241
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 28, 2021
    Inventors: MENG-PING KAO, PENG YIN, OSCAR DIVORRA ESCODA
  • Patent number: 11151724
    Abstract: An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Ping Kao, Ching-Hsing Hsieh, Chia-Chi Chang, Ju-Te Chen, Chen-Hui Huang, Cheng-Hsien Chen
  • Patent number: 11089337
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 10, 2021
    Assignee: INTERDIGITAL VC HOLDINGS, INC.
    Inventors: Meng-Ping Kao, Peng Yin, Oscar Divorra Escoda
  • Publication number: 20210159625
    Abstract: A connector includes a connector housing forming a receptacle configured to receive an add-in card. The connector further includes a first connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The first connector pin extends from the connector housing to contact a first solder pad disposed on a printed circuit board (PCB). The connector further includes a second connector pin configured to electrically couple to the add-in card responsive to the add-in card being inserted into the receptacle. The second connector pin extends from the connector housing to contact a second solder pad disposed on the PCB. The first connector pin is oriented toward the second connector pin to couple to the PCB in a toe-routing configuration and the second connector pin is oriented away from the first connector pin to couple to the PCB in the toe-routing configuration.
    Type: Application
    Filed: April 24, 2020
    Publication date: May 27, 2021
    Inventors: Se-Jung MOON, Chien-Ping KAO, Gaudencio HERNANDEZ SOSA, Beom-Taek LEE
  • Publication number: 20200380693
    Abstract: An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.
    Type: Application
    Filed: June 3, 2019
    Publication date: December 3, 2020
    Inventors: Tzu-Ping KAO, Ching-Hsing HSIEH, Chia-Chi CHANG, Ju-Te CHEN, Chen-Hui HUANG, Cheng-Hsien CHEN
  • Patent number: 10114437
    Abstract: A portable device is provided. A first processor performs an initial procedure according to an operation clock with a first frequency value and an operation voltage with a first voltage value, and performs a calibration procedure according to the operation clock with a second frequency value and the operation voltage with a second voltage value when the initial procedure has been performed and a self-calibration event is present. A second processor detects whether a specific function of the calibration procedure is being performed by the first processor. The second processor stores the second frequency value and the second voltage value into a storage unit after the calibration procedure is performed. The second voltage value is lower than the first voltage value, and the second frequency value is lower than the first frequency value.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: October 30, 2018
    Assignee: MEDIATEK INC.
    Inventors: Yi-Chang Zhuang, Lee-Kee Yong, Wu-an Kuo, Yi-Ping Kao, Alice Wang, Uming Ko
  • Patent number: 10048742
    Abstract: The present invention provides an integrated circuit. The integrated circuit comprises: a plurality of core power sources; and a plurality of core power domains, coupled to the core power sources, respectively; wherein the core power domains are overlapped with each other.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: August 14, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chih-Ching Lin, Yi-Ping Kao, Chun-Sung Su
  • Patent number: 9912111
    Abstract: A receptacle connector includes an insulative housing defining a base and a mating tongue extending from the base with a widen and thicken step structure formed around a root of the mating tongue near to the base, two rows of plate contacts disposed in the insulative housing with contacting sections exposed upon the mating tongue and in front of the step structure and categorized with signal contacts, power contacts and grounding contacts, and a metallic shielding plate disposed within a middle level of the mating tongue and occupying most portions of said mating tongue. The shielding plate defines a pair of immoveable and un-deflectable lateral edge sections in front of the step structure, each lateral edge section is configured to be adapted to be locked with a latch of a plug connector in a transverse direction.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 6, 2018
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Terrance F. Little, Chih-Pi Cheng, Chien-Ping Kao, Wei-Hao Su, An-Jen Yang, De-Cheng Zou, Chih-Hsien Chou, Yuan Zhang
  • Publication number: 20170238021
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 17, 2017
    Inventors: MENG-PING KAO, PENG YIN, OSCAR DIVORRA ESCODA
  • Patent number: 9713736
    Abstract: A dumbbell with detachable weights has a handle assembly, multiple weights, a first end cap assembly, and a second end cap assembly. The handle assembly has a main support with a handle, a first end panel, and a second end panel. The weights are mounted between the first and second end panels of the main support, are arranged around the handle, and are radially detachable from the main support. The first and second end cap assemblies are respectively mounted on the first and second end panels and selectively engage with the weights. By turning a driving cap of the first end cap assembly, the first and second end cap assemblies can disengage from the weights. Since the weights can be radially mounted onto or detached from the main support, an adjusting range of the training weight of the dumbbell can be increased.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 25, 2017
    Inventor: Chien-Ping Kao
  • Patent number: 9674556
    Abstract: There are provided methods and apparatus for in-loop artifact filtering. An apparatus includes an encoder for encoding an image region. The encoder has at least two filters for successively performing in-loop filtering to respectively reduce at least a first and a second type of quantization artifact.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Thomson Licensing
    Inventors: Meng-Ping Kao, Peng Yin, Oscar Divorra Escoda
  • Publication number: 20170050073
    Abstract: A dumbbell with detachable weights has a handle assembly, multiple weights, a first end cap assembly, and a second end cap assembly. The handle assembly has a main support with a handle, a first end panel, and a second end panel. The weights are mounted between the first and second end panels of the main support, are arranged around the handle, and are radially detachable from the main support. The first and second end cap assemblies are respectively mounted on the first and second end panels and selectively engage with the weights. By turning a driving cap of the first end cap assembly, the first and second end cap assemblies can disengage from the weights. Since the weights can be radially mounted onto or detached from the main support, an adjusting range of training weight of the dumbbell can be increased.
    Type: Application
    Filed: August 19, 2015
    Publication date: February 23, 2017
    Inventor: Chien-Ping Kao