Patents by Inventor Ping-Lin Yang

Ping-Lin Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIGITAL LOGIC CIRCUITS HAVING A PULSE WIDTH TIMING CIRCUIT
    Publication number: 20110080201
    Abstract: A pulse width timing includes a first complementary resistor-capacitor (RC) circuit having an input for receiving an input signal, and a second complementary RC circuit coupled to an output of the first complementary RC circuit, wherein the first and second complementary RC circuits cooperate to produce an output signal based on the input signal, the output signal being delayed and having an adjusted pulse width with respect to the input signal.
    Type: Application
    Filed: October 7, 2009
    Publication date: April 7, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Lin Yang, Yi-Tzu Chen
  • Power-down circuit with self-biased compensation circuit
    Patent number: 7760009
    Abstract: A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 20, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Lin Yang, Hsin-Hsin Ko, Chung-Cheng Chou
  • POWER-DOWN CIRCUIT WITH SELF-BIASED COMPENSATION CIRCUIT
    Publication number: 20100141330
    Abstract: A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the gated-node from the first power supply voltage. A second control device is coupled between the first power supply node and the gated-node. The second control device is configured to pass a gated-voltage to the gated-node or disconnect the gated-node from the gated-voltage. A voltage-drop device is coupled between the first power supply node and the gated-node, wherein the voltage-drop device is serially connected with the second control device. A negative-feedback current source is connected in parallel with the voltage-drop device. The negative-feedback current source is configured to provide a current tracking a variation of the gated-voltage at the gated-node.
    Type: Application
    Filed: December 4, 2008
    Publication date: June 10, 2010
    Inventors: Ping-Lin Yang, Hsin-Hsin Ko, Chung-Cheng Chou