Patents by Inventor Ping Lin

Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11663953
    Abstract: Provided are a driver chip, a display screen and a display device. The driver chip is configured to drive a silicon-based display screen, and the driver chip is composed of a bridge chip and a screen driver chip. A signal interface circuit of a first signal processing circuit in the bridge chip receives video signals of each frame of picture. A drive controller controls video signals of P pixels among the video signals of one frame of picture to be output at a first preset transmission speed to a second signal processing circuit of the screen driver chip each time. A signal processor of the second signal processing circuit in the screen driver chip converts the video signals of all of the P pixels into data drive signals and outputs at a second preset transmission speed data drive signals of Q pixels in one frame of picture to a data processing circuit each time.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 30, 2023
    Assignee: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-Lin Liu, Yanfu Huang, Zhenyong Gao
  • Patent number: 11659547
    Abstract: A method of a user equipment (UE) in a wireless communication network and a UE are provided. The method includes receiving, from the network, a downlink (DL) transmission, determining, by the UE, whether to cancel at least a portion of the DL transmission, and cancelling, by the UE, at least the portion of the DL transmission when the UE determines that the portion of the DL transmission is to be cancelled.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 23, 2023
    Inventors: Jung Hyun Bae, Hsien-Ping Lin
  • Publication number: 20230154414
    Abstract: Provided are a source driving circuit, a display device and a pixel driving method. The source driving circuit includes a voltage isolation circuit, a voltage follower circuit, a first voltage dividing circuit, a second voltage dividing circuit, a first switch circuit, a second switch circuit, a third switch circuit, a fourth switch circuit, a fifth switch circuit, a sixth switch circuit and a current source.
    Type: Application
    Filed: March 26, 2021
    Publication date: May 18, 2023
    Applicant: SeeYa Optronics Co., Ltd.
    Inventors: Ping-Lin Liu, Haodong Zhang
  • Patent number: 11652077
    Abstract: A light-emitting display unit including first to third metal layers, first to second insulation layers and micro light-emitting devices is provided. The first metal layer has conductive patterns. The second metal layer has transfer patterns. The third metal layer has pad patterns. The second metal layer is located between the first metal layer and the third metal layer. A distribution density of the first metal layer is less than that of the second metal layer, and greater than that of the third metal layer. The first insulation layer is disposed between the first metal layer and the second metal layer. The second insulation layer is disposed between the second metal layer and the third metal layer. The micro light-emitting devices are disposed on one side of the first metal layer away from the second metal layer, and electrically bonded to the conductive patterns. A display apparatus adopting the light-emitting display unit is also provided.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: May 16, 2023
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Po-Jen Su, Wei-Ping Lin
  • Patent number: 11647623
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes providing a substrate having a first top surface; forming an isolation region in the substrate to surround an active region; forming a recess in the active region; disposing a first conductive material within the recess to form a buried power line and a buried signal line; forming a first circuit layer and a second circuit layer on the first top surface of the substrate, wherein the first circuit layer covers the buried power line and the buried signal line, and the second circuit layer is separated from the first circuit layer; and forming a cell capacitor over the first circuit layer.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: May 9, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Tseng-Fu Lu, Jeng-Ping Lin
  • Publication number: 20230132954
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives, at a time point, DCI scheduling two or more downlink data channels. The UE receives, within a threshold processing time from the time point, a first control signal in a first CORESET according to a first TCI state. The threshold processing time is allocated for the UE to decode the downlink control information. The UE receives, subsequent to the first CORESET, data according to the first TCI state (a) until an end of the threshold processing time when a second CORESET in which the UE is configured to receive a second control signal does not exist in the threshold processing time or (b) until the second CORESET when the second CORESET exists in the threshold processing time.
    Type: Application
    Filed: October 18, 2022
    Publication date: May 4, 2023
    Inventors: Hsien-Ping Lin, Gyu Bum Kyung, Jiann- Ching Guey
  • Patent number: 11640883
    Abstract: A key module includes a bracket, a circuit film assembly, a keycap, and a connecting structure. The bracket includes a bottom plate and a bracket pivotal portion protruding from the bottom plate. The circuit film assembly is disposed on the bracket and includes a plurality of film layers and a supporting portion formed by at least one of the film layers. The supporting portion is located beside the bracket pivotal portion. The keycap is disposed above the bracket and the circuit film assembly and includes a keycap pivotal portion. The connecting structure is disposed between the bracket and the keycap and includes a first pivot pivotally disposed at the bracket pivotal portion and a second pivot pivotally disposed at the keycap pivotal portion. The supporting portion beside the bracket pivotal portion supports the first pivot, such that the first pivot continuously contacts the bracket pivotal portion.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: May 2, 2023
    Assignee: Chicony Electronics Co., Ltd.
    Inventors: Shin-Chin Weng, Chin-Ping Lin, Shih-Yu Hsu, Chih-Feng Chen
  • Patent number: 11633695
    Abstract: A device and method of simultaneously removing flammable gases and nitrous oxide are provided. The device includes a thermal oxidation chamber, a high-temperature resistant dust filter, and a catalyst chamber. The thermal oxidation chamber is configured to receive an exhaust gas from a process tool. The exhaust gas includes flammable gases and nitrous oxide. The thermal oxidation chamber has a first exhaust pipe to emit nitrous oxide and dust generated after the exhaust gas is thermally oxidized. The high-temperature resistant dust filter receives dust and nitrous oxide from the first exhaust pipe, wherein the high-temperature resistant dust filter has a filter fiber net and a second exhaust pipe, and the second exhaust pipe is configured to emit nitrous oxide. The catalyst chamber receives nitrous oxide from the second exhaust pipe, wherein the catalyst chamber has a nitrous oxide decomposition catalyst to decompose nitrous oxide into nitrogen and oxygen.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 25, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Chuan-Lin Chang, Hong-Ping Lin, Shou-Nan Li, Jui-Hsiang Cheng, Hui-Ya Shih, I-Ling Nien
  • Patent number: 11635088
    Abstract: A cooling fan creating a more stable airflow for heat-removing purposes, with reduced noise of operation, comprises a rotor hub and preferably an odd number of blades mounted on periphery of the rotor hub in unequal intervals. Adjacent blades are configured with different shapes, reducing the noise generated during operation without affecting the cooling effect.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: April 25, 2023
    Assignee: CHAMP TECH OPTICAL (FOSHAN) CORPORATION
    Inventors: Xiao-Guang Ma, Zheng Luo, Yung-Ping Lin, Yong-Kang Zhang
  • Patent number: 11632610
    Abstract: A speaker module includes a base, a speaker and a wire. The base has a bottom and a first wire fixing portion. The speaker is disposed in the base and has a second wire fixing portion. The wire is fixed to the first wire fixing portion and the second wire fixing portion to suspend the speaker in the base, and the speaker is separated from the bottom with a distance. A projection device having the speaker module is further provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: April 18, 2023
    Assignee: Coretronic Corporation
    Inventors: Chao-Kuan Wu, Wei-Ping Lin
  • Publication number: 20230116161
    Abstract: A method for performing PDCCH monitoring of component carriers (CCs) in a carrier aggregation scheme that aggregates a first CC and a second CC. In some embodiments, the method includes: calculating a first monitoring occasion start time for a monitoring occasion of the first CC, wherein the first monitoring occasion start time is expressed as a first symbol-index value; calculating a second monitoring occasion start time for a monitoring occasion of the second CC, wherein the second monitoring occasion start time is expressed as a second symbol-index value; and generating a schedule for the monitoring occasion of the first CC and the monitoring occasion of the second CC based on an ascending order of the first monitoring occasion start time and the second monitoring occasion start time.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 13, 2023
    Inventors: Hsien-Ping LIN, Jung Hyun BAE
  • Patent number: 11626949
    Abstract: A method of a user equipment (UE) in a wireless communication network and a UE are provided. The method includes receiving, from the network, at least one downlink (DL) transmission, determining, by the UE, channel resource information reference signal (CSI-RS) occasions in the at least one DL transmission, determining, by the UE, whether a power of each of the CSI-RS occasions is the same, and averaging, by the UE, corresponding measurements when the power of each of the CSI-RS occasions is determined to be the same.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 11, 2023
    Inventors: Jung Hyun Bae, Hsien-Ping Lin
  • Publication number: 20230106840
    Abstract: Systems and methods for automatically configuring a firewall are described. Systems and methods include receiving one or more flows, automatically detecting elements of a computing environment, automatically generating a firewall configuration based on the detected elements of the computing environment and the received one or more flows, and automatically configuring a firewall within the computing environment with the firewall configuration.
    Type: Application
    Filed: September 28, 2021
    Publication date: April 6, 2023
    Inventors: Lin Lin, Ping Lin
  • Patent number: 11619845
    Abstract: This disclosure relates to a display device which includes a light transmissible layer and a second material. The light transmissible layer includes a first material, wherein the first material generates a first color transformation from a first color to a second color after being exposed under a light of the first wavelength range. The second material is either included in the light transmissible layer or has a projective area overlapped with the light transmissible layer. The second material generates a second color transformation from the second color to the first color after being exposed under a light of the first wavelength range.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 4, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Shih-Ping Lin
  • Publication number: 20230098830
    Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Patent number: 11615991
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11614762
    Abstract: A voltage converter comprises a current mirror circuit, a switch circuit, and a bias circuit electrically connected to a substrate of the switch circuit. When an electrical signal provided by the first electrical signal end is greater than an electrical signal provided by the second electrical signal end, the bias circuit is turned on to turn on the switch circuit, thereby an output end of the mirror current circuit outputs the electrical signal provided by the second electrical signal end. Otherwise, the output end of the current mirror circuit outputs the second voltage signal.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 28, 2023
    Assignee: SeeYA Optronics Co., Ltd.
    Inventors: Ping-Lin Liu, Chih-Pu Yeh
  • Patent number: 11610897
    Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 21, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
  • Patent number: 11605346
    Abstract: The present disclosure describes a display panel and a circuit to generate a data signal current included thereof. The circuit further comprises a signal voltage module to generate a primary signal voltage and send to a second storage capacitor in a control module to output a data signal voltage. The second storage capacitor is coupled to a first storage capacitor and a gate of a current output transistor, so that the primary signal voltage is stored at the joint node. A threshold voltage of the current output transistor, generated by a voltage compensation module, is then added on to the gate of the current output transistor, so that an output current compensated by the threshold voltage is realized.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: March 14, 2023
    Assignee: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-Lin Liu, Haodong Zhang
  • Patent number: 11596450
    Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 7, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Kuo-Yi Yang, Yi-Hung Wen, Wei-Lun Fan, Fang-Jie Jang, Shih-Ping Lin