Patents by Inventor Ping Lin

Ping Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11632610
    Abstract: A speaker module includes a base, a speaker and a wire. The base has a bottom and a first wire fixing portion. The speaker is disposed in the base and has a second wire fixing portion. The wire is fixed to the first wire fixing portion and the second wire fixing portion to suspend the speaker in the base, and the speaker is separated from the bottom with a distance. A projection device having the speaker module is further provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: April 18, 2023
    Assignee: Coretronic Corporation
    Inventors: Chao-Kuan Wu, Wei-Ping Lin
  • Publication number: 20230116161
    Abstract: A method for performing PDCCH monitoring of component carriers (CCs) in a carrier aggregation scheme that aggregates a first CC and a second CC. In some embodiments, the method includes: calculating a first monitoring occasion start time for a monitoring occasion of the first CC, wherein the first monitoring occasion start time is expressed as a first symbol-index value; calculating a second monitoring occasion start time for a monitoring occasion of the second CC, wherein the second monitoring occasion start time is expressed as a second symbol-index value; and generating a schedule for the monitoring occasion of the first CC and the monitoring occasion of the second CC based on an ascending order of the first monitoring occasion start time and the second monitoring occasion start time.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 13, 2023
    Inventors: Hsien-Ping LIN, Jung Hyun BAE
  • Patent number: 11626949
    Abstract: A method of a user equipment (UE) in a wireless communication network and a UE are provided. The method includes receiving, from the network, at least one downlink (DL) transmission, determining, by the UE, channel resource information reference signal (CSI-RS) occasions in the at least one DL transmission, determining, by the UE, whether a power of each of the CSI-RS occasions is the same, and averaging, by the UE, corresponding measurements when the power of each of the CSI-RS occasions is determined to be the same.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 11, 2023
    Inventors: Jung Hyun Bae, Hsien-Ping Lin
  • Publication number: 20230106840
    Abstract: Systems and methods for automatically configuring a firewall are described. Systems and methods include receiving one or more flows, automatically detecting elements of a computing environment, automatically generating a firewall configuration based on the detected elements of the computing environment and the received one or more flows, and automatically configuring a firewall within the computing environment with the firewall configuration.
    Type: Application
    Filed: September 28, 2021
    Publication date: April 6, 2023
    Inventors: Lin Lin, Ping Lin
  • Patent number: 11619845
    Abstract: This disclosure relates to a display device which includes a light transmissible layer and a second material. The light transmissible layer includes a first material, wherein the first material generates a first color transformation from a first color to a second color after being exposed under a light of the first wavelength range. The second material is either included in the light transmissible layer or has a projective area overlapped with the light transmissible layer. The second material generates a second color transformation from the second color to the first color after being exposed under a light of the first wavelength range.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: April 4, 2023
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Shih-Ping Lin
  • Publication number: 20230098830
    Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.
    Type: Application
    Filed: December 8, 2022
    Publication date: March 30, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Da TSAI, Cheng-Ping LIN, Wei-Hung LIN, Chih-Wei LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Patent number: 11615991
    Abstract: An embodiment method includes: forming fins extending from a semiconductor substrate; depositing an inter-layer dielectric (ILD) layer on the fins; forming masking layers on the ILD layer; forming a cut mask on the masking layers, the cut mask including a first dielectric material, the cut mask having first openings exposing the masking layers, each of the first openings surrounded on all sides by the first dielectric material; forming a line mask on the cut mask and in the first openings, the line mask having slot openings, the slot openings exposing portions of the cut mask and portions of the masking layers, the slot openings being strips extending perpendicular to the fins; patterning the masking layers by etching the portions of the masking layers exposed by the first openings and the slot openings; and etching contact openings in the ILD layer using the patterned masking layers as an etching mask.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Yuan Chen, Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11614762
    Abstract: A voltage converter comprises a current mirror circuit, a switch circuit, and a bias circuit electrically connected to a substrate of the switch circuit. When an electrical signal provided by the first electrical signal end is greater than an electrical signal provided by the second electrical signal end, the bias circuit is turned on to turn on the switch circuit, thereby an output end of the mirror current circuit outputs the electrical signal provided by the second electrical signal end. Otherwise, the output end of the current mirror circuit outputs the second voltage signal.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 28, 2023
    Assignee: SeeYA Optronics Co., Ltd.
    Inventors: Ping-Lin Liu, Chih-Pu Yeh
  • Patent number: 11610897
    Abstract: Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 21, 2023
    Assignee: Winbond Electronics Corp.
    Inventors: Keng-Ping Lin, Tetsuharu Kurokawa, Tzu-Ming Ou Yang, Shu-Ming Li
  • Patent number: 11605346
    Abstract: The present disclosure describes a display panel and a circuit to generate a data signal current included thereof. The circuit further comprises a signal voltage module to generate a primary signal voltage and send to a second storage capacitor in a control module to output a data signal voltage. The second storage capacitor is coupled to a first storage capacitor and a gate of a current output transistor, so that the primary signal voltage is stored at the joint node. A threshold voltage of the current output transistor, generated by a voltage compensation module, is then added on to the gate of the current output transistor, so that an output current compensated by the threshold voltage is realized.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: March 14, 2023
    Assignee: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-Lin Liu, Haodong Zhang
  • Patent number: 11596450
    Abstract: A low-profile offset-type spinal fusion device includes a first screw, a connection base, a nut and a compression part. The first screw has an external thread and a flange. The connection base includes a penetration part and a connection part disposed no higher than the penetration part, and can sleeve the first screw through a first hole of the penetration part to contact the flange with opposite ends of the first screw protruding out of the first hole. The nut, used to engage the first screw, has a bottom surface to contact against the penetration part. When the first screw is installed by penetrating the first hole, the nut and the flange are located to opposite ends of the first hole. The compression part is to screw into a cavity of the connection part for depressing a connecting bar tightly in the cavity.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: March 7, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsin-Hsin Shen, Pei-I Tsai, Chih-Chieh Huang, Kuo-Yi Yang, Yi-Hung Wen, Wei-Lun Fan, Fang-Jie Jang, Shih-Ping Lin
  • Publication number: 20230061857
    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members, a second plurality of channel members, a first gate structure over and wrapping around each of the first plurality of channel members, a second gate structure over and wrapping around each of the second plurality of channel members, and a frontside source contact disposed between the first plurality of channel members and the second plurality of channel members as well as between the first gate structure and the second gate structure.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Jui-Ping Lin, Kai-Di Tzeng, Chen-Ming Lee, Wei-Yang Lee
  • Publication number: 20230066613
    Abstract: Provided are a pixel driving circuit, a method for driving the pixel driving circuit, a silicon-based display panel and a display device. The pixel driving circuit is used for driving a light-emitting element to emit light. At an initial stage, a reset circuit provides a reset signal to a third node; a light emission control transistor is in a first on state to transmit the reset signal to a second node; a threshold compensation circuit transmits the reset signal to a first node; and a data write circuit transmits a non-enable level Vofs of a data signal to a second terminal of a first capacitor. At a threshold compensation stage, the threshold compensation circuit provides a threshold voltage of a drive transistor to the first node for compensation.
    Type: Application
    Filed: July 15, 2022
    Publication date: March 2, 2023
    Applicant: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-lin LIU, Tong WU
  • Publication number: 20230059771
    Abstract: An optical measurement system is provided, which includes a light source device, a fiber module, an optical detection device and a processing circuit. The light source device is configured to generate light to illuminate a target tissue area and a reference tissue area of a human body. The fiber module is configured to direct and transmit the light to illuminate the target tissue area and the reference tissue area and receive response beams from the target tissue area and the reference tissue area. The optical detection device is configured to detect the response beams from the target tissue area to obtain the target spectrum signal and detect the response beams from the reference tissue area to obtain a reference spectrum signal. The processing circuit configured to calculate a health status parameter of the target tissue area according to the target spectrum signal and reference spectrum signal.
    Type: Application
    Filed: April 13, 2022
    Publication date: February 23, 2023
    Applicant: Advanced ACEBIOTEK CO., LTD.
    Inventors: Yi-Ping Lin, Jyh-Chern Chen, Shen-Fu Hsu
  • Publication number: 20230048669
    Abstract: Provided are a driver chip, a display screen and a display device. The driver chip is configured to drive a silicon-based display screen, and the driver chip is composed of a bridge chip and a screen driver chip. A signal interface circuit of a first signal processing circuit in the bridge chip receives video signals of each frame of picture. A drive controller controls video signals of P pixels among the video signals of one frame of picture to be output at a first preset transmission speed to a second signal processing circuit of the screen driver chip each time. A signal processor of the second signal processing circuit in the screen driver chip converts the video signals of all of the P pixels into data drive signals and outputs at a second preset transmission speed data drive signals of Q pixels in one frame of picture to a data processing circuit each time.
    Type: Application
    Filed: March 26, 2021
    Publication date: February 16, 2023
    Applicant: SEEYA OPTRONICS CO., LTD.
    Inventors: Ping-Lin LIU, Yanfu HUANG, Zhenyong GAO
  • Publication number: 20230052616
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The UE receives an indication of a number of slots in a slot group. The UE receives a configuration associated with a duration indicating a number of slot groups in which down link control channels are to be monitored by the UE. The UE receives an indication indicating one or more slots, in each slot group in the duration, in which search spaces are located for detecting the down link control channels. The UE searches the search spaces in the one or more slots in each slot group in the duration to detect the down link control channels.
    Type: Application
    Filed: July 12, 2022
    Publication date: February 16, 2023
    Inventor: Hsien-Ping Lin
  • Publication number: 20230049425
    Abstract: A manufacturing method of a memory structure including the following steps is provided. A substrate is provided. The substrate includes a memory array region. A bit line structure is formed in the memory array region. The bit line structure is located on the substrate. A contact structure is formed in the memory array region. The contact structure is located on the substrate on one side of the bit line structure. A stop layer is formed in the memory array region. The stop layer is located above the bit line structure. A capacitor structure is formed in the memory array region. The capacitor structure passes through the stop layer and is electrically connected to the contact structure. The bottom surface of the capacitor structure is lower than the bottom surface of the stop layer.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Applicant: Winbond Electronics Corp.
    Inventors: Keng-Ping Lin, Shu-Ming Li, Tzu-Ming Ou Yang
  • Publication number: 20230049041
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. In certain configurations, the UE receives DCI scheduling two or more downlink data channels to be transmitted in one or more slots. The UE determines an indication, in the DCI, indicating a first TCI state and a second TCI state. The UE receives each of the two or more downlink data channels in a respective first set of resources in accordance with the first TCI state and in a respective second set of resources in accordance with the second TCI state.
    Type: Application
    Filed: July 12, 2022
    Publication date: February 16, 2023
    Inventors: Hsien-Ping Lin, Gyu Bum Kyung
  • Patent number: 11578728
    Abstract: A fan module including a body and a plurality of blades is provided. The body has a rotating axis and the body is telescopic along the rotating axis to have an elongated state and a shortened state. The blades are respectively disposed on the body and rotate along with the body along the rotating axis. At least a portion of each blade is flexible and a bending state of each blade is changed along with the elongated state or the shortened state of the body. An axial size of each blade along the rotating axis when the body is in the elongated state is greater than the axial size of each blade along the rotating axis when the body is in the shortened state.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 14, 2023
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Han-Hsuan Tsai, Jui-Min Huang, Wei-Hao Lan, Chien-Chu Chen, Ching-Ya Tu, Chih-Wen Chiang, Ching-Tai Chang, Ken-Ping Lin, Yao-Lin Chang, Cheng-Ya Chi
  • Publication number: 20230043726
    Abstract: The application discloses a bonding method, a display backplane and a system for manufacturing the display backplane. The method includes: providing a substrate, and forming a plurality of first metal bumps on the substrate; providing a transfer device to transfer the plurality of the first metal bumps to a TFT substrate to form a plurality of pairs of metal pads on the TFT substrate, wherein each pair of the metal pads include two of the first metal bumps; and providing a plurality of LED flip chips, and transferring the plurality of LED flip chips to the TFT substrate by using the transfer device to bond electrodes of each of the LED flip chips to one pair of the metal pads respectively.
    Type: Application
    Filed: April 30, 2020
    Publication date: February 9, 2023
    Inventors: Shoujun XIAO, Tzu-ping LIN, Shan-Fu YUAN, Liu-chung LEE, Chung-yu CHOU