Abstract: A method of manufacturing semiconductor packages is proposed. A die carrier is provided having a plurality of substrate units. At least one semiconductor die is mounted on each substrate unit by an adhesive. Then the die carrier mounted with the dies is cured in a jig fixture. The jig fixture has a submold and at least one exhaust passage communicated with an external exhauster. Air in the jig fixture is drawn out by the external exhauster through the exhaust passage to form a negative-pressure environment in the jig fixture. The negative-pressure environment generates an attraction force to secure the dies to the submold and counteract thermal stresses produced in the die carrier, thereby preventing die cracking, warpage and delamination from occurrence, such that the planarity of the die carrier is assured and solder balls can be precisely secured to the die carrier in position.

Abstract: A semiconductor package and a method for fabricating the same are proposed. A chip has an active surface, and an opposing non-active surface. A plurality of conductive elements are mounted on the active surface and electrically connected to the chip. A first encapsulant is formed on the active surface of the chip, for encapsulating the active surface and conductive elements, wherein end portions of the conductive elements are exposed to outside of the first encapsulant, and adapted to be recessed in position with respect to an exposed surface of the first encapsulant. A plurality of conductive media are implanted at end portions of the conductive elements, allowing the chip to be electrically connected to an external device by the conductive elements and conductive media. A second encapsulant is formed on the non-active surface of the chip, and cooperates with the first encapsulant to provide mechanical strength for the semiconductor package.

Abstract: A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: A semiconductor package with a heat sink is provided, having a substrate formed with at least one opening penetrating therethrough. A heat sink is mounted on a surface of the substrate same as for forming solder balls and seals one end of the opening by a thermally conductive adhesive. At least one chip is mounted on the other surface of the substrate opposite to the heat sink via the thermally conductive adhesive and covers the other end of the opening. The thermally conductive adhesive is filled in the opening between the substrate and the heat sink and allows heat produced by the chip to be dissipated through a shorter thermally conductive path. By the above arrangement with the heat sink being mounted between the chip and an external device, the heat sink provides electromagnetic shielding between the chip and the external device and enhances electrical performance of the semiconductor package.

Abstract: A stacked flipchip package is disclosed comprising two chip carriers, each of which includes at least a chip and a plurality of solder bumps formed on the active surface of the chip used to electrically connect the chip to the chip carrier. A first chip carrier is joined “back to back” with a second chip carrier via an insulating adhesive applied on the inactive surface of the first chip mounted on the first chip carrier and the inactive surface of the second chip mounted on the second chip carrier. Wherein the two inactive surfaces are bonded together to form a multichip module. Both the topmost surface and the lowermost surface of the multichip module are capable of being electrically connected with other components, thereby eliminating one of the obstacles associated with vertically stacking chips in flip-chip technology and further varying arrangement flexibility of the chips in a package.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: A semiconductor package with a reinforced substrate and a fabrication method of the substrate are provided. The substrate is formed of a metal core layer with relatively high rigidity, and an insulating layer is coated on at least a surface of the core layer. At least a ground via is formed through the insulating layer, allowing a chip mounted on the substrate to be electrically connected and grounded to the substrate by the ground via. The reinforced substrate provides the semiconductor package with sufficient mechanical strength, and can be reduced in thickness in favor of package profile miniaturization. Moreover, the substrate made of the metal core layer and insulating layer has a relatively small dielectric constant to facilitate electron transmission velocity, thereby improving electrical quality of the semiconductor package. Furthermore, the metal core layer is made of a thermally-conductive metallic material, and enhances heat dissipating efficiency of the semiconductor package.

Abstract: A semiconductor package and a method for fabricating the same are proposed. A chip has an active surface, and an opposing non-active surface. A plurality of conductive elements are mounted on the active surface and electrically connected to the chip. A first encapsulant is formed on the active surface of the chip, for encapsulating the active surface and conductive elements, wherein end portions of the conductive elements are exposed to outside of the first encapsulant, and adapted to be recessed in position with respect to an exposed surface of the first encapsulant. A plurality of conductive media are implanted at end portions of the conductive elements, allowing the chip to be electrically connected to an external device by the conductive elements and conductive media. A second encapsulant is formed on the non-active surface of the chip, and cooperates with the first encapsulant to provide mechanical strength for the semiconductor package.

Abstract: A test fixture for semiconductor packages is provided. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein, wherein each through hole is formed with a positioning mechanism that is engaged with a corresponding semiconductor package received in the through hole, so as to allow the semiconductor package to be firmly held in position within the through hole. The covering member is attached to the interposer, and provided with elastic mechanisms for assuring the semiconductor packages in electrical contact with the circuit board. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a first circuit board, a second circuit board, an interposer and a covering member. The first and second circuit boards are used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device, in a manner that the second circuit board is interposed between the semiconductor packages and the first circuit board. The interposer is mounted on the second circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: A test method and a test device for integrated circuits are proposed. The test device includes: a test platform having a plurality of spaced-apart test tunnels; a test tray defined with board attach areas corresponding in position to the test tunnels, whereby a strip board having a plurality of semiconductor packages can be placed on a board attach area, and aligned with a corresponding test tunnel; and a control mechanism for gradually moving the test tray to perform tests for the semiconductor packages on the strip board. In operation of the test method, first, a plurality of strip boards having semiconductor packages are placed on the test tray, and each corresponds to a test tunnel of the test platform. Then, the test tray is gradually moved in a manner as to perform tests for all semiconductor packages on the strip board step by step.

Abstract: A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: An inspection device for the position of trademark on integrated circuit board is disclosed. The inspection device comprises an inspection plate made from a transparent acrylic material having a plurality of inspection engraving lines thereon and a plurality of position holes; and a base seat having mounted with a plurality of position pegs which correspond to the position holes on the inspection plate; thereby a pin platform for inspection is positioned between the base seat and the inspection plate and the inspection line is corresponding to the trademark on the surface of the integrated circuit (IC) to proceed with the inspection.

Abstract: An inspection device for wiring of integrated circuit includes a base seat and an inspection cover, wherein the top end of the base seat is provided with cavity of appropriate depth and having supporting rib, and the two lateral sides of the cavity are provided with protruded edge a little higher than the cavity; the inspection cover having two side blocks is provided with an extended frame stripe such that the two side blocks and the two frame stripes are formed into a frame body, and corresponding stripes are formed between the two side blocks such that the corresponding stripes divides the frame body into a plurality of observation region, and each observation region is adapted for an inspection plate made from a transparent material, and the two side withholding seat of the inspection plate are located at the end face of the two side blocks, and the inspection plate moves along the end face of the two side blocks, whereby the base plate of the IC is positioned at the withholding protruded edge of the base

Abstract: A system, method, and apparatus for changing the functional mode of a telephone terminal in a private branch exchange (PBX) is presented. A user can issue a command via the keypad indigenous to a telephone terminal, causing the telephone terminal to transmit a request to an interface module, requesting a change in the functional mode of operation of the requesting phone. The interface module responds by causing the software module supporting the current functional mode of operation of the telephone terminal to terminate the logical software link to the telephone terminal and causing the software module supporting the requested functional mode of operation to establish a logical software link to the telephone terminal, thereby changing the functional mode of operation of the telephone terminal.

Abstract: A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAMs makes use of a double-layered polysilicon structure and a phosphoric acid etching. When the double-layered polysilicon structure is etched with the phosphoric acid, the polysilicon grain boundary is etched at a rate faster than the polysilicon grain itself so as to enable the formation of a rugged surface and thus increases the total surface area.

Abstract: A computerized exercise game machine provides continuous and instantaneous feedback to the exerciser or user to maintain the user's exercise goal in real time. The exercise goal is updated by the computer system each time the user uses the exercise game machine. The machine includes a fixed frame and moveable component. A signal is generated in response to the speed of movement of the moveable component. The user or exerciser is prompted to maintain a video object representing the user within a shadow object or domain on the video screen. The shadow object represents the exercise goal, such as running at five miles per hour. Different video objects are utilized for users of different physical fitness levels. A shadow object (domain) or course environment is associated with each different video object. The game machine may also provide feedback to the exercise device to control the speed of movement or resistance to movement, slope, such as raising or lowering a treadmill or curve simulation.

Abstract: A method of fabricating a super thin O/N/O stacked dielectric by oxidizing a thin nitride layer in low pressure oxygen for high-density DRAMs is disclosed. A thin nitride layer with a thickness of approximately 20 .ANG. to 60 .ANG. is formed over the surface of a silicon substrate. The nitride layer is oxidized in pure oxygen ambient of 0.01 Torr to 76 Torr at a temperature from 750.degree. C. to 950.degree. C. for approximately 10 to 60 minutes. A super thin oxide/nitride/oxide (O/N/O) stacked dielectric exhibiting a low leakage current and high reliability for use in high-density DRAMs is formed by the aforementioned low-pressure dry-oxidation procedure.