Abstract: The present invention provides a factory power management and control method based on edge-cloud coordination, including: 1) forming an industrial field network by a field node, a routing node and a device executing production tasks; 2) parsing production task information data and sending; 3) issuing an STN model in production field to an edge node; 4) sending to the edge node; 5) computing, required to complete the production tasks; 6) computing values of comprehensive ranks; 7) executing, by the edge node, the higher rank, and executing, by the cloud power management center, the lower rank; 8) executing, by the edge node, a demand response algorithm; 9) executing, by the production device, the production tasks based on computing results; and executing, by a power generation station in factory, a power storage station in factory and a power supply station outside factory, corresponding schemes based on the results.

Abstract: A user requests explanation of a term. In response, a definition is provided. The user can indicate that the user does not understand a new term included in the definition. In response, explanation information is customized based on analysis of the initial term and the new term, and then the explanation information is provided to the user.

Abstract: Disclosed are a method and device for assisting a smart device in network communication. The method comprises: at least one smart device is connected to a gateway device by means of a wired connection so that the network device, an assisting terminal, and the at least one smart device are in a same local area network, a TCP connection between the at least one smart device and the assisting terminal is established via the gateway device; the assisting terminal receives a network production request comprising meal production information transmitted by a server, transforms the network production request into a TCP production instruction applicable for the at least one smart device, and transmits to the corresponding smart device, thus allowing the corresponding smart device to complete a corresponding operation on the basis of the TCP production instruction.

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a first gate structure disposed on the substrate, a second gate structure disposed on the substrate, and a memory gate structure disposed on the substrate and between the first gate structure and the second gate structure. The memory gate structure at least covers the first gate structure and the second gate structure. The memory gate structure includes a charge storage layer disposed on the substrate and a memory gate layer disposed on the charge storage layer.

Abstract: The present disclosure relates to the technical field of water-based acrylic resin coatings, in particular to a method for creating a water-based acrylic resin coating with high water resistance. It includes the following steps: selecting a commercially available water-based acrylic resin paint; mixing the water-based acrylic resin paint and ethyl acetate to obtain solution A, spraying solution A on a surface of a material or immersing the material in solution A, and then solidifying; mixing lye and a silver precursor solution to obtain solution B; immersing the cured material in solution B and then drying the cured material.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

Abstract: The present invention relates generally to compositions and methods for mutating a plant and plants and plant products produced by said methods. Also, compositions and methods for controlling a plant species are disclosed herein.

Abstract: An endoscopic system includes a single-use portion and a multiple-use portion. The two portions can be mated and un-mated. The single-use portion includes an elongated cannula that has a bendable section near its distal end providing a “steerable” distal tip. The distal tip includes LED illumination and an imaging module that feeds live video to a display screen forming which forms part of the multiple-use portion. Ergonomically designed steering control and significant portions of the steering structure reside in the multiple-use portion. The cannula is configured to rotate, which further expands the field of view when combined with steering deflection along a single axis. Some embodiments, include motorized distal tip deflection and/or omni-directional tip deflection.

Abstract: A semiconductor package includes a redistribution layer structure, a first semiconductor chip, a circuit board structure and an encapsulation layer. The redistribution layer structure has a first side and a second side opposite to the first side. The first semiconductor chip is electrically connected to the first side of the redistribution layer structure. The circuit board structure is electrically connected to the first side of the redistribution layer structure, and the circuit board structure includes a first mask layer having an opening pattern that corresponds to first semiconductor chip. The encapsulation layer laterally encapsulates the circuit board structure and fills in a space between the semiconductor chip and the opening pattern of the first mask layer of the circuit board structure.

Abstract: This invention relates to NPC-1 antigen on the MUC5AC protein and 16C3 antigen on CEACAM5 and CEACAM6 proteins, and 31.1 epitope on the A33 protein are differentially expressed in cancers including, lung cancer, ovarian cancer, pancreas cancer, breast cancer, and colon cancer, and diagnostic and therapeutic usages. Further, NPC-1, 16C3, and/or 31.1 epitope specific antibodies and diagnostic and therapeutic methods of use.

Abstract: A semiconductor device with isolation structures of different dielectric constants and a method of fabricating the same are disclosed. The semiconductor device includes fin structures with first and second fin portions disposed on first and second device areas on a substrate and first and second pair of gate structures disposed on the first and second fin portions. The second pair of gate structures is electrically isolated from the first pair of gate structures. The semiconductor device further includes a first isolation structure interposed between the first pair of gate structures and a second isolation structure interposed between the second pair of gate structures. The first isolation structure includes a first nitride liner and a first oxide fill layer. The second isolation structure includes a second nitride liner and a second oxide fill layer. The second nitride liner is thicker than the first nitride liner.

Abstract: A keyboard device includes a bottom cover, a supporting plate, a flexible circuit board and plural key structures. The supporting plate is installed on the bottom cover. The supporting plate has a curved arc-shaped profile that is bent upwardly in a direction away from the bottom cover. The supporting plate includes plural perforations. The flexible circuit board is arranged between the bottom cover and the supporting plate. The plural key structures are installed on the supporting plate. The plural key structures are penetrated through the corresponding perforations and contacted with the flexible circuit board.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an insulation encapsulation, and at least one first through interlayer via. The first redistribution structure includes a dielectric layer, a feed line at least partially disposed on the dielectric layer and a signal enhancement layer covering the feed line, wherein the signal enhancement layer has a lower dissipation factor (DO and/or a lower permittivity (Dk) than the dielectric layer. The die is disposed on the first redistribution structure. The insulation encapsulation encapsulates the die. The at least one first TIV is embedded in the insulation encapsulation and the signal enhancement layer.

Abstract: The disclosure provides a semiconductor memory device including a substrate having a memory cell region and an alignment mark region; a dielectric layer covering the memory cell region and the alignment mark region; conductive vias in the dielectric layer within the memory cell region; an alignment mark trench in the dielectric layer within the alignment mark region; and storage structures disposed on the conductive vias, respectively. Each of the storage structures includes a bottom electrode defined from a bottom electrode metal layer, a magnetic tunnel junction (MTJ) structure defined from an MTJ layer, and a top electrode. A residual metal stack is left in the alignment mark trench. The residual metal stack includes a portion of the bottom electrode metal layer and a portion of the MTJ layer.

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

Abstract: In an in-memory database management system, non-volatile random access memories (NVRAMs) are used to store database data and control data. Because this data is stored in NVRAM, the data survives system failures. Recovery from a system failure may be accomplished more quickly by, at least in part, modifying the surviving data in NVRAM, rather than loading an entire checkpoint image and applying uncheckpointed transactions needed to synchronize the database. Because in this form of recovery the database state that serves as the starting point for applying change records is the database as stored in the NVRAM, this form of recovery is referred to herein as in-memory-based recovery. Recovery, where the database state that serves as the starting point for applying change records is a checkpoint image, is referred to herein as checkpointed-based recovery. In-memory-based recovery eliminates or reduces the need to perform certain operations that are performed for checkpointed-based recovery.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.

Abstract: An endoscopic system includes a single-use portion and a multiple-use portion. The two portions can be mated and un-mated. The single-use portion includes an elongated cannula that has a bendable section near its distal end providing a “steerable” distal tip. The imaging system includes at least two separate cameras and two separate light sources. The camera and light sources are configured to simultaneously image a target object. By employing different illuminations, different filters and manipulating the spectral responses, different characteristics of the target object can be captured. According to some embodiments, a system processor can coordinate the cameras, the light sources and combine the resulting images to display to an operator an enhanced combined image the object.

Abstract: An endoscope in which a reusable part is inserted into a sheath of a single-use portion that includes a needle with an imaging module at its tip and a part of the reusable portion that is not covered by the sheath is covered with a flexible cap that initially was sterile and covered the open end of the sheath, whereby the entire reusable portion is covered and sealed from the environment by the cap and the sheath during a medical procedure.

Abstract: Microstructure enhanced photodector arrangements uses a CMOS image sensor (CIS) wafer of crystalline Si and a CMOS Logic Processor (CLP) wafer stacked on each other for electrical interaction. The wafers can be fabricated separately and stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays are enhanced with microstructure holes. Avalanche photodiodes, single photon avalanche photodiodes and phototransistors can be laterally and/or vertically doped. Photodetectors/photosensors can have slanted sidewalls for improved optical confinement and reduced crosstalk.