Patents by Inventor Ping Wang

Ping Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220354973
    Abstract: A method may include wet ball milling a plurality of iron nitride nanoparticles in the presence of a surface active agent to modify a surface of the plurality of iron nitride nanoparticles and form a plurality of surface-modified iron nitride nanoparticles for a variety of biomedical applications and soft magnetic materials related applications.
    Type: Application
    Filed: April 20, 2022
    Publication date: November 10, 2022
    Inventors: Jian-Ping Wang, Kai Wu, Bin Ma, Jinming Liu
  • Publication number: 20220359977
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20220359206
    Abstract: A gate stack can be etched to form a trench extending through the gate stack, the trench removing a portion of the gate stack to separate the gate stack into a first gate stack portion and a second gate stack portion. A dielectric material is deposited in the trench to form a dielectric region, the dielectric region having an air gap in the dielectric material. The air gap may extend upward from beneath the gate stack to an area interposed between the end of the first gate stack portion and the end of the second gate stack portion. Contacts to the first gate stack portion and contacts to the second gate stack portion may be formed which are electrically isolated from each other by the dielectric material and air gap formed therein.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Ting-Gang Chen, Wan-Hsien Lin, Chieh-Ping Wang, Tai-Chun Huang, Chi On Chui
  • Publication number: 20220360174
    Abstract: A basic unit for a power converter, a power converter, and a universal power interface are disclosed. The basic unit includes an inductor, a power half-bridge, a first terminal, a second terminal, a third terminal, and a fourth terminal, where an end of the inductor is connected to a midpoint of the power half-bridge, and the other end of the inductor is connected to the first terminal; a source terminal of a lower bridge arm of the power half-bridge is connected to the second terminal and the fourth terminal; and a drain terminal of an upper bridge arm of the power half-bridge is connected to the third terminal. The manufacturing costs of a microgrid system and the difficulty of later maintenance can be reduced.
    Type: Application
    Filed: August 31, 2021
    Publication date: November 10, 2022
    Inventors: Yifeng WANG, Xiaoyong MA, Ping WANG, Long TAO, Pengyu CHENG, Ningyi LIANG, Danfeng ZHAO
  • Publication number: 20220348749
    Abstract: The present invention relates to a molded article with a sufficiently metallic appearance and a sufficient degree of brightness.
    Type: Application
    Filed: March 31, 2022
    Publication date: November 3, 2022
    Inventors: Fang Chen, Fangyu Cheng, Wenlong Pang, Zhan Cheng, Ruizhi Pei, Zihui Xu, Ping Wang
  • Publication number: 20220353195
    Abstract: A scheduling method applied in an industrial heterogeneous network in which a TSN and a non-TSN are interconnected is provided. The TSSDN controller classifies data flows according to the delay requirements, and calculates the scheduling priorities of the data flows in the industrial heterogeneous network. The TSSDN controller adopts an improved CSPF algorithm to determine a shortest path in the heterogeneous network, and marks the scheduling priorities of the data flows which are transmitted from the subnet of the heterogeneous network and arrive at the switch for the first time. Flow table matching is performed at the SDN switch. In a case of performing flow table matching successfully, the counter is updated and the instruction included in the flow table is executed. In a case of performing flow table matching unsuccessfully, a PacketIn message is transmitted to the TSSDN controller, and the TSSDN controller performs analysis and makes a decision.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 3, 2022
    Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Min WEI, XueQin XIANG, Ping WANG, XianChun YAN
  • Publication number: 20220347194
    Abstract: Inhibition of EphB receptors (e.g., EphB1) can be used in therapeutic methods for treating EphB receptor-associated conditions (e.g., pain, cancer). Demeclocycline, chlortetracycline, and minocycline are identified as EphB receptor inhibitors. Accordingly, aspects of the disclosure relate to methods for treating pain comprising providing demeclocycline, chlortetracycline, minocycline, or derivatives thereof, alone or in combination, to an individual in need thereof. Further aspects relate to pharmaceutical compositions comprising two or more of minocycline, demeclocycline, chlortetracycline, and/or derivatives thereof.
    Type: Application
    Filed: September 18, 2020
    Publication date: November 3, 2022
    Inventors: MAHMOUD SALMA AHMED, ENAS KANDIL, HESHAM SADEK, PING WANG, ROBERT BACHOO, MARK HENKEMEYER
  • Patent number: 11489947
    Abstract: A relay node and method for encapsulating a packet based on a tunneling protocol. The relay node includes a communication device, a storage device, and a processor. The communication device communicates with a receiving node and a transmitting node; the storage device stores multiple instructions; and the processor is coupled to the communication device and the storage device for loading and executing the multiple instructions stored in the storage device to: control the communication device to receive a packet transmitted by the transmitting node; generate a protocol header related to the packet based on the packet, and calculate a checksum as a checksum block in the multiple sections using multiple sections in the protocol header at least; generate an encapsulated packet including the protocol header and the packet; and transmit the encapsulated packet to the receiving node through the communication device for verifying the checksum block.
    Type: Grant
    Filed: November 27, 2020
    Date of Patent: November 1, 2022
    Assignee: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jing-Ping Wang, Wen-Yao Chang
  • Patent number: 11490397
    Abstract: Embodiments are presented herein for adjusting the conduct of routine communications of safety messages in V2X networks in order to conserve resources in participating power-limited devices while satisfying V2X system latency demands. Scheduling (e.g., timing and/or frequency) of safety message communications performed by certain UE devices participating in a V2X network may be dynamically adjusted according to various criteria, such as factors relating to the DRX cycle schedule, motion or mobility, traffic environment, and/or battery or power capabilities of the UE devices, which may conserve UE resources and power consumption. Certain UE devices may efficiently transmit safety messages to the V2X network using one of several proposed RACH-based procedures. In some embodiments, the size of safety message communications may be reduced through various compression techniques, and/or by reducing the amount of contained information, e.g.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: November 1, 2022
    Assignee: Apple Inc.
    Inventors: Wanping Zhang, Sachin J. Sane, Faraz Faheem, Wei Zhang, Dawei Zhang, Wei Zeng, Haitong Sun, Yuqin Chen, Haijing Hu, Ping Wang
  • Patent number: 11483341
    Abstract: The present invention relates to a DDoS attack detection and mitigation method for an industrial SDN network, and belongs to the field of network security. According to the method, by means of the cooperation between an east-west interface of an SDN controller in an industrial backhaul network and a system manager of an industrial access network, in conjunction with the features of the industrial backhaul network and an industrial access network data packet, a flow entry matching field of an OpenFlow switch is extended, and a flow table 0 is set to be a “flow table dedicated to DDoS attack mitigation” for defending against an attacking data flow in a timely manner. By using the SDN controller of an industrial backhaul network and a DDoS attack detection and mitigation system, an attacking data flow is identified and a DDoS attack source is found, and the policy of mitigating a DDoS attack is implemented by means of scheduling a system manager of the industrial access network.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 25, 2022
    Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Min Wei, Tao Yang, Jiuchao Mao, Qiaoyue Pang, Ping Wang
  • Patent number: 11482387
    Abstract: A membrane circuit board includes a first film substrate, a second film substrate, an insulating spacer substrate and a waterproof structure. The first circuit layer is installed on the first film substrate. A second circuit layer is installed on the second film substrate. The insulating spacer substrate arranged between the first film substrate and the second film substrate. The first circuit layer is arranged between the first film substrate and the insulating spacer substrate. The second circuit layer is arranged between the second film substrate and the insulating spacer substrate. The waterproof structure includes a first welding layer and a second welding layer. The first welding layer is arranged between the first film substrate and the insulating spacer substrate. The second welding layer is arranged between the second film substrate and the insulating spacer substrate.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: October 25, 2022
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Liu-Bing Cai, Li-Xiong Deng, Fu-Zhou Wei, Li-Qiang Chen, Xiao-Ping Wang
  • Publication number: 20220336631
    Abstract: A device includes a first III-V compound layer, a second III-V compound layer, source and drain structures, a gate structure, and a gate field plate. The second III-V compound layer is over the first III-V compound layer. The source and drain structures are over the second III-V compound layer and spaced apart from each other. The gate structure is over the second III-V compound layer and between the source and drain structures. The gate field plate is over the second III-V compound. From a top view the gate field plate forms a strip pattern interposing a stripe pattern of the gate structure and a stripe pattern of the drain structure.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jheng-Sheng YOU, Hsin-Chih LIN, Kun-Ming HUANG, Lieh-Chuan CHEN, Po-Tao CHU, Shen-Ping WANG, Chien-Li KUO
  • Publication number: 20220336606
    Abstract: A memory cell includes a substrate. A first STI and a second STI are embedded within the substrate. The first STI and the second STI extend along a first direction. An active region is disposed on the substrate and between the first STI and the second STI. A control gate is disposed on the substrate and extends along a second direction. The first direction is different from the second direction. A tunneling region is disposed in the active region overlapping the active region. A first trench is embedded within the tunneling region. Two second trenches are respectively embedded within the first STI and the second STI. The control gate fills in the first trench and the second trenches. An electron trapping stack is disposed between the tunneling region and the control gate.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Hao Pan, Chi-Cheng Huang, Kuo-Lung Li, Szu-Ping Wang, Po-Hsuan Chen, Chao-Sheng Cheng
  • Publication number: 20220336386
    Abstract: A package structure includes a chip package and an antenna package. The chip package includes at least one semiconductor die and a first insulating encapsulation encapsulating the at least one semiconductor die. The antenna package is located on and electrically coupled to the chip package. The antenna package includes metallic patterns embedded in a second insulating encapsulation, wherein each of the metallic patterns has a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface, wherein the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation, and the second surface is levelled and coplanar with a third surface of the second insulating encapsulation. A method of manufacturing a package structure is also provided.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Han-Ping Pu, Yen-Ping Wang
  • Publication number: 20220336735
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Wei Chen, Po-Kai Hsu, Yu-Ping Wang, Hung-Yueh Chen
  • Publication number: 20220330286
    Abstract: A user equipment device may determine whether to power down one or more components based at least on a scheduling parameter that includes an indication of cross-slot scheduling. The device may power down the one or more components prior to decoding control information during a slot for which the scheduling parameter indicates that cross-slot scheduling is in place.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: Jia Tang, Wei Zhang, Wei Zeng, Haitong Sun, Yuchul Kim, Ping Wang, Sreevalsan Vallath, Zhu Ji, Dawei Zhang
  • Publication number: 20220328757
    Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 13, 2022
    Inventors: Duarte José Pereira de Sousa, Cesar Octavio Ascencio, Jian-Ping Wang, Tony Low
  • Publication number: 20220320020
    Abstract: Provided is a package structure and a method of forming the same. The package structure includes a semiconductor package, a stacked patch antenna structure, and a plurality of conductive connectors. The semiconductor package includes a die. The stacked patch antenna structure is disposed on the semiconductor package, and separated from the semiconductor package by an air cavity. The plurality of conductive connectors is disposed in the air cavity between the semiconductor package and the stacked patch antenna structure to connect the semiconductor package and the stacked patch antenna structure.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Yi Hsu, Kai-Chiang Wu, Yen-Ping Wang
  • Publication number: 20220313840
    Abstract: The present application relates to ligands targeted to epidermal growth factor receptor (EGFR) and compositions for use in treating tumors. Specifically, a ligand targeted to EGFR is disclosed. The ligand comprises a heavy chain variable domain and a light chain variable domain. The ligand may be selected from the group consisting of a single chain variable fragment, a fusion protein, a monoclonal antibody, and an antigen-binding fragment thereof. The ligand may be conjugated to a liposome or a nanoparticle that encapsulates at least one chemotherapeutic agent to form a ligand-targeted liposomal or nanoparticle drug. Also disclosed are conjugates and formulations for use in treating tumors such as squamous cell carcinoma of head and neck. A method for making a ligand-targeted liposomal drug is also disclosed. The drug may be a chemotherapeutic agent selected from the group consisting of doxorubicine and vinorelbine.
    Type: Application
    Filed: May 31, 2020
    Publication date: October 6, 2022
    Inventors: Han-Chung WU, Yi-Ping WANG, I-Ju LIU, Meng-Jhe CHUNG
  • Publication number: 20220321355
    Abstract: The present invention relates to a judgment method for edge node computing result trustworthiness based on trust evaluation, and belongs to the technical field of data processing. By means of the present invention, a security mechanism for trustworthiness of a computing result output by an industrial edge node is guaranteed, the industrial edge node is prevented from outputting error data, and attacks of false data of malicious edge nodes are resisted, it is guaranteed that trustworthy computing results not be tampered are input in the industrial cloud, and a site device is made to receive correct computing results rather than malicious or meaningless messages, thereby improving efficiency and security of industrial production.
    Type: Application
    Filed: July 15, 2020
    Publication date: October 6, 2022
    Applicant: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS
    Inventors: Min Wei, Er Xiong Liang, Ping Wang