Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: Method of successively depositing a multi-film is disclosed. An electric charge removing process is performed after a deposition process of the last film of the multi-film or between the two neighboring film deposition processes. The electric charge removing process includes introducing an inert gas into a reaction chamber of the deposition system and pumping out the inert gas from the reaction chamber.

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: A method for fabricating a metal-insulator-metal capacitor is described. A first metal layer is formed on a substrate. A plasma treatment is performed on the surface of the first metal layer. Then, a first oxide layer, a nitride layer and a second oxide layer are formed in sequence over the first metal layer. Thereafter, a second metal layer is formed on the second oxide layer. The second metal layer, the second oxide layer, the nitride layer, the first oxide layer and the first metal layer are defined to form the metal-insulator-metal capacitor.

Abstract: An infrared imaging sensor and a vacuum packaging method thereof are described. The infrared imaging sensor includes a ceramic base, a metal cap and an infrared filter. The ceramic base has an infrared imaging chip attached thereon and the metal cap includes a getter deposited on an inner surface of the metal cap. The infrared filter seals an opening of the metal cap. The ceramic base, the metal cap and the infrared filter are heated in a vacuum chamber to activate the getter, and to solder the ceramic base, the metal cap and the infrared filter together thereby vacuum packaging the infrared imaging sensor.

Abstract: A method for gap filling between metal-metal lines is provided so that a first dielectric layer forms on a surface and side wall of a plurality of metal lines thereon which is called partially HDP deposition. Then, a portion of the first dielectric layer is removed by a high-density plasma with Ar/O2 to sputter so that a portion of side wall of metal lines is exposed. Afterwards, a second dielectric layer is formed on the first dielectric layer by a method of high density plasma oxide deposition so that the metal lines are completely covered.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

Abstract: A method of fabricating a well-filled STI Structure in a semiconductor substrate. A trench is formed in the semiconductor substrate. A liner oxide and a liner nitride are formed on the bottom and sidewall of the trench subsequently. A HDP oxide layer is deposited in the trench conformally to fill a portion of the trench. A layer of poly-silicon is deposited over the HDP oxide layer conformally. The semiconductor substrate is subjected to a thermal treatment to oxidize the poly-silicon. The surface of the semiconductor substrate is planarized to form a shallow trench isolation structure. The trench is well filled by the oxidized poly-silicon and the HDP oxide without voids and seams.

Abstract: A method of forming shallow trench isolation (STI) in a substrate. A shield layer is formed on part of the substrate. Using the shield layer as a mask, part of the substrate is removed to form a trench in the substrate. A first insulation layer is formed in part of the trench, where the trench remains an opening. The first insulation layer is partially etched back to leave a remaining first insulation layer at the bottom of the trench and to expose the sidewall of the trench above the remaining first insulation layer. The trench is filled up with a second insulation layer extending onto the shield layer. A planarization is performed on the second insulation layer, where the shield layer serves as a stop layer for the planarization. Thus, a void-free trench isolation area is formed in a substrate.

Abstract: An apparatus for depositing an insulation layer in a trench. A wafer loader is used to load a wafer having a trench. A first HDP-CVD chamber adjoins the wafer loader, where the first HDP-CVD chamber is used to deposit a first insulation layer in the trench, and the first trench retains an opening. A vapor-etching chamber adjoins the first HDP-CVD chamber. The vapor-etching chamber is used to remove part of the first insulation layer to leave a remaining first insulation layer at the bottom of the trench and expose the sidewall of the trench above the remaining first insulation layer. A second HDP-CVD chamber adjoins the vapor-etching chamber, where the second HDP-CVD chamber fills the trench by depositing a second insulation layer. A wafer unloader adjoins the second HDP-CVD chamber.

Abstract: A method of fabricating a void-free barrier layer located on a semiconductor substrate. First, conductive structures are defined on the semiconductor substrate. Second, a barrier layer is deposited over the conductive structures, wherein the barrier layer has a void between the conductive structures. Third, argon gas is introduced into a HDPCVD chamber to sputter the barrier layer so that the void is eliminated.

Abstract: A method for improving gate oxide thinning issue at trench corners is disclosed. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. As a consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried achieved to accomplish the gate oxide formation.

Abstract: An HDPCVD oxide layer is deposited over metal lines on a semiconductor substrate. The HDPCVD oxide layer so deposited has ridged portions over the metal lines. The HDPCVD oxide layer is then treated in-situ with an inert gas or reactive gas plasma to remove the ridged portions on the surface. A sacrificial dielectric layer can then be deposited on the HDPCVD oxide layer with good step coverage, thereby to eliminate voids.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Abstract: A method for improving trench isolation is disclosed. A trench is etched into the substrate by using a photo mask. A bottom oxide layer, a sidewall oxide layer and a polycrystalline silicon layer are deposited into the trench and over the wafer, and are etched to clear from the surface, then over-etched till a recess is formed within the trench. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, an oxidation step is utilized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent stress problem induced by a wedge shaped oxide growing in the space between the plug and the substrate.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.