Abstract: An HDPCVD oxide layer is deposited over metal lines on a semiconductor substrate. The HDPCVD oxide layer so deposited has ridged portions over the metal lines. The HDPCVD oxide layer is then treated in-situ with an inert gas or reactive gas plasma to remove the ridged portions on the surface. A sacrificial dielectric layer can then be deposited on the HDPCVD oxide layer with good step coverage, thereby to eliminate voids.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: An irradiation process method for forming polysilicon layer is disclosed. The method includes firstly forming an alpha-silicon layer on substrate. Then the temperature of the UHV-CVD chamber is increased and the wafer is sent into the chamber. Gas is then intermittently conducted into the vacuum-chamber apparatus. While increasing the temperature of the vacuum-chamber apparatus, the whole throughput thus increases and the process-time for the polysilicon layer thus decreases. Finally, the electrical capacity thus increases by forming the polysilicon layer.

Abstract: A method for improving trench isolation is disclosed. A trench is etched into the substrate by using a photo mask. A bottom oxide layer, a sidewall oxide layer and a polycrystalline silicon layer are deposited into the trench and over the wafer, and are etched to clear from the surface, then over-etched till a recess is formed within the trench. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, an oxidation step is utilized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent stress problem induced by a wedge shaped oxide growing in the space between the plug and the substrate.

Abstract: A method for planarizing a polycrystalline silicon layer deposited on a trench, which is formed on a semiconductor substrate, comprises the following steps. First, a polycrystalline silicon layer with an enough thickness is deposited on the surface of the semiconductor substrate to overfill the trench. At least one dimple is undesirably developed on the polycrystalline silicon layer during the polycrystalline silicon deposition. Then, an oxide layer with an enough thickness is formed on the polycrystalline silicon layer to overfill the at least one dimple. Next, the polycrystalline silicon layer is partially oxidized so as to transform the upper portion thereof into a polysilicon oxide layer. As a result of a non-uniform distribution of the oxidization rate, the bottom surface of the polysilicon oxide layer, i.e. the interface between the polysilicon oxide layer and the non-oxidized portion of the polycrystalline silicon layer, is substantially planar.

Abstract: The present invention relates to a method for forming rugged polysilicon capacitance electrodes uses for dynamic random access memory processes is disclosed. The method is capable in reducing process time, enhancing yield, and saving production cost. Wherein, the process of the present invention comprises: firstly, a semiconductor wafer is delivered into a low pressure chemical vapor deposition (LPCVD) tube. Herein, a non-doped or doped amorphous silicon layer is deposited on the surface top of electrodes. A rugged polysilicon capacitance is formed on top of the non-doped or doped amorphous silicon layer by using the methods of rising temperature and decreasing pressure. Then, an ion implantation is applied and follows by a wafer cleaning procedure and an annealing process, wherein those procedures are accomplished after the removal of the wafer from LPCVD tube.

Abstract: A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Abstract: The present invention provides a method for enlarging the surface area of hemi-spherical grains on the surface of a semiconductor chip. The hemi-spherical grain structure is formed by combining a poly-silicon layer with an underlying amorphous silicon layer. In processing, the two layers are etched with a corrosive solution that etches the amorphous silicon layer at a higher rate than it etches the poly-silicon layer. In this way, a ring-shaped slot forms at the bottom of each hemi-spherical grain thus increasing the total surface area of the hemi-spherical grain structure. Furthermore, surface area of the storage node is increased and the cell capacitor capacitance increases in excess of 15%.