Patents by Inventor Ping Xu

Ping Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10050130
    Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 14, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Publication number: 20180177185
    Abstract: In one aspect, the present invention relates to a composition for delivery of double stranded RNA to an insect having a basic pH within its alimentary canal, wherein the composition comprises double stranded RNA adsorbed onto a clay complex, and wherein the clay complex is configured to release the double stranded RNA at the basic pH. Other aspects of the invention relate to preparations including the composition of the invention, methods of delivering double stranded RNA to an insect and methods of protecting a crop against an insect.
    Type: Application
    Filed: June 17, 2016
    Publication date: June 28, 2018
    Inventors: Neena MITTER, Zhi Ping XU
  • Publication number: 20180166283
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes providing a base substrate including a substrate and a plurality of discrete fins on the substrate; forming a support layer at least partially on sidewalls of the fins; ion implanting the fins through the support layer to form an ion doped region by an ion implantation process; removing the support layer to expose sidewalls of the fins.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 14, 2018
    Inventors: Guo Bin YU, Xiao Ping XU
  • Publication number: 20180145182
    Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.
    Type: Application
    Filed: November 22, 2017
    Publication date: May 24, 2018
    Inventors: Guo Bin YU, Xiao Ping XU
  • Patent number: 9867574
    Abstract: A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 16, 2018
    Assignee: National University of Singapore
    Inventors: Kian Ann Ng, Yong Ping Xu, Shih-Cheng Yen, Nitish V. Thakor
  • Publication number: 20170300112
    Abstract: A method, apparatus and system for controlling a smart device based on a headphone are disclosed. The method includes: collecting, by the headphone, head motion feature data of a human body if a trigger condition of a collection task is satisfied; judging, according to the collected data, whether a target motion feature satisfying a predetermined motion feature is present in head motion feature of the human body; and if the target motion feature is present, acquiring information of an application currently running on the smart device, and generating an operation control instruction corresponding to the target motion feature according to the information of the currently running application and sending the operation control instruction to the smart device. According to the present application, control function may be enhanced for the smart device and control accuracy may be improved.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: Luming ZHOU, Hexing LIU, Saiwen LU, Ping XU, Hongwu LI, Yicong LIN
  • Publication number: 20170238876
    Abstract: A high CMRR neural signal amplifier is configured for supply rail common mode feedback (SR-CMFB) whereby a set of CMFB signals is provided to supply rails of front end LNAs. High CMRR is maintained through buffering outputs of front end signal LNAs and a reference LNA coupled to signal and reference inputs of second stage amplifiers, respectively; and buffering the reference LNA output using an active/guard buffer pair, whereby across a plurality of distinct multiplexing time intervals, during each multiplexing time interval one buffer of the pair functions as an active buffer that drives second stage amplifier reference inputs corresponding to second stage amplifier outputs being multiplexed to a set of multiplexor outputs, and the other buffer of the pair functions as a guard buffer coupled to other second stage amplifier reference inputs corresponding to second stage amplifier outputs not being multiplexed to the set of multiplexor outputs.
    Type: Application
    Filed: February 22, 2016
    Publication date: August 24, 2017
    Inventors: Kian Ann NG, Yong Ping Xu, Shih-Cheng Yen, Nitish V. Thakor
  • Publication number: 20170229560
    Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.
    Type: Application
    Filed: January 5, 2017
    Publication date: August 10, 2017
    Inventors: Guo Bin YU, Xiao Ping XU
  • Patent number: 9658894
    Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for reclaiming resources during virtual machine decommission. The method includes determining a virtual machine (VM) resource utilization and a cluster utilization. If the VM resource utilization is less than a first predetermined threshold and the cluster utilization is greater than a second predetermined threshold, the method then determines whether an active timer exists. If the active timer exists and has expired, then dynamic decommission of the VM is triggered.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yong Feng, Heng Ping Xu, Ying Nan Zhang, Yu Zhang
  • Publication number: 20170109211
    Abstract: Embodiments of the present invention provide a method, computer program product, and computer system for reclaiming resources during virtual machine decommission. The method includes determining a virtual machine (VM) resource utilization and a cluster utilization. If the VM resource utilization is less than a first predetermined threshold and the cluster utilization is greater than a second predetermined threshold, the method then determines whether an active timer exists. If the active timer exists and has expired, then dynamic decommission of the VM is triggered.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Yong Feng, Heng Ping Xu, Ying Nan Zhang, Yu Zhang
  • Publication number: 20170109204
    Abstract: Embodiments of the present invention relate to CPU resource management in a computer cluster. A master node selects a CPU core of at least one compute node for an application from a computer cluster, and allocates a portion of resource of the CPU core to the application. The master node re-allocates a new portion of the resource of the CPU core to the application, in response to a trigger event for re-allocation.
    Type: Application
    Filed: October 15, 2015
    Publication date: April 20, 2017
    Inventors: Kuan Feng, Fan Jie Meng, Heng Ping Xu, Ting Xue
  • Patent number: 9608656
    Abstract: Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 28, 2017
    Assignee: National University of Singapore
    Inventors: Chao Yuan, Kian Ann Ng, Yong Ping Xu
  • Publication number: 20170033800
    Abstract: Analog-to-digital converter (ADC) circuitry includes a first binary-weighted capacitor array having a total capacitance of 2n-2C. The value of n represents number of bits of a digital signal that represents an analog signal. The ADC circuitry also includes a second binary-weighted capacitor array having a total capacitance of 2n-2C. In addition to that, the ADC circuitry further includes a comparator circuit having first and second terminals. The first terminal is coupled to the first binary-weighted capacitor array, and the second terminal is coupled to the second binary weighted capacitor array. The switching circuit within the second binary-weighted capacitor array may be configurable to couple a largest capacitance capacitor within the second binary-weighted capacitor array from remaining capacitors within the second binary weighted capacitor array.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 2, 2017
    Inventors: Chao Yuan, Kian Ann Ng, Yong Ping Xu
  • Publication number: 20170029819
    Abstract: Aspects of the present invention relate to a plant-protecting RN Ai composition comprising plant-protecting double-stranded RNA adsorbed onto Layered Double Hydroxide (LDH) particles, and to methods for protecting a plant comprising the step of administering to a plant an RNAi composition comprising plant-protecting double-stranded RNA adsorbed onto LDH particles.
    Type: Application
    Filed: March 14, 2014
    Publication date: February 2, 2017
    Inventors: Neena MITTER, Zhi Ping XU, Gao Qing LU
  • Publication number: 20160168210
    Abstract: Compounds of interest, for example active pharmaceutical ingredients, probes or inactive carriers, may be delivered to a site of interest by conjugating the compound of interest to a collagen-binding linear hairpin (CBLH) peptide to form a molecule of Formula (I) and then providing the molecule to the site of interest where the CBLH peptide binds to collagen at the site of interest thereby delivering the compound of interest to the site of interest.
    Type: Application
    Filed: October 18, 2013
    Publication date: June 16, 2016
    Applicant: NATIONAL RESEARCH COUNCIL OF CANADA
    Inventors: Feng NI, Ping XU, Sazzad HOSSAIN, Dmitri TOLKATCHEV, Louis-Philippe RICHER
  • Publication number: 20160158458
    Abstract: An injection needle assembly includes a needle extended from a needle seat and a lockable needle arrangement which includes a locking platform radially extended from the needle seat, a needle enclosure foldably extended from the locking platform for enclosing the needle, and a locker unit including a first locker provided at the locking platform and a second locker provided at the needle enclosure, wherein the first and second lockers are engaged in a non-releasable manner to securely lock up the needle enclosure on the locking platform for ensuring the needle to be enclosed within the needle enclosure. Therefore, after the use of the needle for injection, the needle is enclosed and protected by the needle enclosure for preventing any cross infection.
    Type: Application
    Filed: December 7, 2014
    Publication date: June 9, 2016
    Inventors: Zhong FENG, Zhiling FENG, Chunyin SU, Liping MIAO, Ping XU, Jingjuan ZHU, Yunfei GU
  • Patent number: 9322049
    Abstract: The invention provides a method of increasing a deacetylated activity of SIRT6 by contacting SIRT6 with an agent that binds SIRT6 and reduces the Km of SIRT6 for a substrate, thereby increasing the deacetylase activity of SIRT6. The invention also provides compounds of the formulas (II) and (III).
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 26, 2016
    Assignee: CORNELL UNIVERSITY
    Inventors: Anthony Sauve, Ping Xu
  • Patent number: 9274274
    Abstract: A photonic chip based on periodical poling and waveguides circuits in ferroelectric crystals, the method is based on the integration of waveguide circuits, periodical poling and electro-optic modulator (EOM). The chip is illustrated by FIG. 1. The waveguide circuits guide the photons and makes linear operations like the beam splitting, filtering etc. on the photons. The periodical poling enables the efficient spontaneous parametric down conversion (SPDC), resulting the generation of entangled photons. The EOM controls the phase of photons dynamically. The following directional coupler distributes the entangled photons and the quantum interference takes place, resulting different types of path-entangled states by controlling the voltage of EOM insides the chip.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: March 1, 2016
    Assignee: Nanjing University
    Inventors: Ping Xu, Hua Jin, Shining Zhu
  • Patent number: 9221926
    Abstract: A functional TFE copolymer fine powder is described, wherein the TFE copolymer is a polymer of TFE and at least one functional comonomer, and wherein the TFE copolymer has functional groups that are pendant to the polymer chain. The functional TFE copolymer fine powder resin is paste extrudable and expandable. Methods for making the functional TFE copolymer are also described. The expanded functional TFE copolymer material may be post-reacted after expansion.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 29, 2015
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Ping Xu, Jack J. Hegenbarth, Xin Kang Chen
  • Patent number: 9221924
    Abstract: A functional TFE copolymer fine powder is described, wherein the TFE copolymer is a polymer of TFE and at least one functional comonomer, and wherein the TFE copolymer has functional groups that are pendant to the polymer chain. The functional TFE copolymer fine powder resin is paste extrudable and expandable. Methods for making the functional TFE copolymer are also described. The expanded functional TFE copolymer material may be post-reacted after expansion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 29, 2015
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Ping Xu, Jack J. Hegenbarth, Xin Kang Chen