Patents by Inventor Ping Yan

Ping Yan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167076
    Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.
    Type: Application
    Filed: February 21, 2020
    Publication date: June 3, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Wenxiang XU, Haohao YANG, Pan HUANG, Ping YAN, Zongliang HUO, Wenbin ZHOU, Wei XU
  • Publication number: 20210167084
    Abstract: A method for forming a three-dimensional (3D) memory device includes forming a cut structure in a stack structure. The stack structure includes interleaved a plurality of initial sacrificial layers and a plurality of initial insulating layers. The method also includes removing portions of the stack structure adjacent to the cut structure to form a slit structure and an initial support structure. The initial support structure divides the slit structure into a plurality of slit openings. The method further includes forming a plurality of conductor portions in the initial support structure through the plurality of slit openings. The method also includes forming a source contact in each of the plurality of slit openings. The method also includes removing portions of the initial support structure to form a support structure. The support structure includes an adhesion portion extending through the support structure.
    Type: Application
    Filed: January 13, 2021
    Publication date: June 3, 2021
    Inventors: Qingqing Wang, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou
  • Publication number: 20210167086
    Abstract: A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions.
    Type: Application
    Filed: February 8, 2021
    Publication date: June 3, 2021
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20210167592
    Abstract: A current limiting circuit for controlling current from a power supply to a load having a capacitance includes an inductor, a transistor coupled in a current path with the inductor, and a control circuit. The transistor includes a control terminal. The control circuit is coupled to sense a voltage across the inductor and coupled to the control terminal of the transistor. The control circuit is configured to turn off the transistor when the voltage across the inductor is greater than a threshold to restrict current from a power supply, and turn on the transistor when a defined parameter is met to allow current from the power supply to charge the load capacitance. Other example current limiting circuits are also disclosed.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 3, 2021
    Inventors: Wei Ping Li, Wei Jia Yan, Wen Jian Liao, Xin Zhang
  • Patent number: 11025652
    Abstract: Architectures and techniques for in-app behavior detection. A behavior detection agent within an application running on a hardware computing device captures events within the application. The events are inputs received from one or more sources external to the application. The behavior detection agent generates an event stream from the captured events. The behavior detection agent analyzes the event stream for significant feature frequencies and associations corresponding to one or more attack profiles. The behavior detection agent initiates an attack response in response to finding one or more significant feature frequencies and associations. The attack response comprises at least changing an operational configuration of the application.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 1, 2021
    Assignee: salesforce.com, inc.
    Inventors: Philip Raymond Nadeau, Tejinder Singh Aulakh, Ping Yan, Huy Nhut Hang
  • Patent number: 11005864
    Abstract: Techniques for user behavior anomaly detection. At least one low-variance characteristic is compared to an expected result for the corresponding low-variance characteristics to determine if the low-variance characteristic(s) is/are within a pre-selected range of the expected results. A security response action is taken in response to the low-variance characteristic not being within the first pre-selected range of the expected results. At least one high-variance characteristic is compared to an expected result for the corresponding high-variance characteristics to determine if the high-variance characteristic(s) is/are within a pre-selected range of the expected results. A security response action is taken in response to the high-variance characteristic not being within the first pre-selected range of the expected results. Access is provided if the low-variance and the high-variance characteristics are within the respective expected ranges.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: May 11, 2021
    Assignee: salesforce.com, inc.
    Inventors: Matthew Saunders, Ping Yan, John Slater, Wei Deng
  • Publication number: 20210118891
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.
    Type: Application
    Filed: December 4, 2020
    Publication date: April 22, 2021
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lei DING, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
  • Publication number: 20210104549
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate.
    Type: Application
    Filed: November 21, 2020
    Publication date: April 8, 2021
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20210104540
    Abstract: Embodiments of a three-dimensional (3D) memory device with a corrosion-resistant composite spacer and method for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of dielectric/sacrificial layer pairs is formed on a substrate. A memory string extending vertically through the dielectric stack is formed. A slit extending vertically through the dielectric stack is formed. A memory stack is formed on the substrate including a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric/sacrificial layer pairs through the slit. A composite spacer is formed along a sidewall of the slit. The composite spacer includes a first silicon oxide film, a second silicon oxide film, and a dielectric film formed laterally between the first silicon oxide film and the second silicon oxide film. A slit contact extending vertically in the slit is formed.
    Type: Application
    Filed: November 21, 2020
    Publication date: April 8, 2021
    Inventors: Bo Xu, Ping Yan, Chuan Yang, Jing Gao, Zongliang Huo, Lu Zhang
  • Publication number: 20210066336
    Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 4, 2021
    Inventors: Qingqing Wang, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou
  • Publication number: 20210066461
    Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The 3D memory device also includes a plurality of channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes a support structure dividing the source structure into first and second sections. The source structure also includes an adhesion layer. At least a portion of the adhesion layer extends through the support structure and conductively connects the first and second sections.
    Type: Application
    Filed: November 20, 2019
    Publication date: March 4, 2021
    Inventors: Zhengliang Xia, Pan Huang, Wei Xu, Ping Yan, Zongliang Huo, Wenbin Zhou
  • Publication number: 20210050367
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure, and two adjacent ones of the plurality of source contacts are conductively connected to one another.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 18, 2021
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Publication number: 20210050366
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack over a substrate, a plurality of channel structures, and a source structure. The memory stack includes interleaved a plurality of conductor layers and a plurality of insulating layers. The plurality of channel structures extend vertically in the memory stack. The source structure extend in the memory stack. The source structure includes a plurality of source contacts each in a respective insulating structure. At least two of the plurality of source contacts are in contact with and conductively connected to one another.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 18, 2021
    Inventors: Pan Huang, Wei Xu, Ping Yan, Wenxiang Xu, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Publication number: 20210050358
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, and a source structure. The memory stack is over a substrate and includes interleaved a plurality of conductor layers and a plurality of insulating layers. The source structure includes a plurality of source contacts, and two adjacent ones of the plurality of source contacts are conductively connected to one another by a connection layer. A pair of first portions of the connection layer are over the two adjacent ones of the plurality of source contacts and a second portion of the connection layer being between the two adjacent ones of the plurality of source contacts. Top surfaces of the pair of first portions of the connection are coplanar with a top surface of the second portion.
    Type: Application
    Filed: October 16, 2019
    Publication date: February 18, 2021
    Inventors: Wenxiang Xu, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou, Ji Xia
  • Publication number: 20200395375
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 17, 2020
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20200395374
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 17, 2020
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20200395376
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a memory stack having interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The 3D memory device also includes a plurality of channel structures extending vertically through the memory stack into the substrate. The 3D memory device further includes at least one slit structure extending vertically and laterally in the memory stack and dividing a plurality of memory cells into at least one memory block, the at least one slit structure each including a plurality of slit openings and a support structure between adjacent slit openings. The support structure may be in contact with adjacent memory blocks and contacting the substrate.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 17, 2020
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Publication number: 20200395373
    Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a memory stack, a plurality of channel structures, a slit structure, and a source structure. The memory stack may be over a substrate and may include interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack. The plurality of channel structures may extend vertically through the memory stack into the substrate. The slit structure may extend vertically and laterally in the memory stack and divide the plurality of memory cells into at least one memory block. The slit structure may include a plurality of protruding portions and a plurality of recessed portions arranged vertically along a sidewall of the slit structure.
    Type: Application
    Filed: October 31, 2019
    Publication date: December 17, 2020
    Inventors: Zongliang Huo, Haohao Yang, Wei Xu, Ping Yan, Pan Huang, Wenbin Zhou
  • Patent number: 10868033
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
  • Patent number: 10857517
    Abstract: A porous chiral material of formula [M(L)1.5(A)]+X? wherein M is a metal ion; L is a nitrogen-containing bidentate ligand; A is the anion of mandelic acid or a related acid; and X? is an anion.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 8, 2020
    Assignees: NANKAI UNIVERSITY, UNIVERSITY OF LIMERICK
    Inventors: Shi-Yuan Zhang, Cheng-Xiong Yang, Wei Shi, Xiu-Ping Yan, Peng Cheng, Michael J. Zaworotko