Patents by Inventor Ping-Ying Wang

Ping-Ying Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189620
    Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Hsu-Yang Wang, Ping-Cheng Hsu, Shih-Fang Tzou, Chin-Lung Lin, Yi-Hsiu Lee, Koji Taniguchi, Harn-Jiunn Wang, Tsung-Ying Tsai
  • Patent number: 10148272
    Abstract: A frequency generating circuit includes: a delay circuit, arranged to operably delay an output frequency signal to generate a delayed signal; a quartz crystal resonator, coupled with the delay circuit, arranged to operably conduct a band-pass filtering operation on the delayed signal to generate the output frequency signal; and a delay control circuit, coupled with the delay circuit, arranged to operably control a phase delay amount of the delay circuit to thereby control the phase of the delayed signal.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: December 4, 2018
    Inventor: Ping-Ying Wang
  • Publication number: 20180323791
    Abstract: A frequency generating circuit includes: a delay circuit, arranged to operably delay an output frequency signal to generate a delayed signal; a quartz crystal resonator, coupled with the delay circuit, arranged to operably conduct a band-pass filtering operation on the delayed signal to generate the output frequency signal; and a delay control circuit, coupled with the delay circuit, arranged to operably control a phase delay amount of the delay circuit to thereby control the phase of the delayed signal.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 8, 2018
    Inventor: Ping-Ying WANG
  • Publication number: 20170111051
    Abstract: A frequency generating circuit includes: a differential delay circuit arranged to operably delay an input signal to generate a first delayed signal and a second delayed signal; a quartz crystal resonator arranged to operably conduct a band-pass filtering operation on one of the first and second delayed signals to generate a frequency signal; a compensation capacitor, coupled between another output of the differential delay circuit and an output of the quartz crystal resonator, arranged to operably suppress noise in the frequency signal; an oscillator arranged to operably generate an oscillating signal under control of a control signal; a frequency divider arranged to operably conduct a frequency-dividing operation on the oscillating signal to generate the input signal; and a feedback control circuit arranged to operably generate the control signal according to the frequency signal.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventor: Ping-Ying WANG
  • Patent number: 9584143
    Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: February 28, 2017
    Assignee: MEDIATEK INC.
    Inventors: Yi-Chieh Huang, Ping-Ying Wang
  • Publication number: 20160211967
    Abstract: A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.
    Type: Application
    Filed: November 17, 2015
    Publication date: July 21, 2016
    Inventors: Yi-Chieh Huang, Ping-Ying Wang
  • Patent number: 9306577
    Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 5, 2016
    Assignee: MEDIATEK INC.
    Inventors: Yi-Chieh Huang, Ping-Ying Wang
  • Patent number: 8952759
    Abstract: A circuit for controlling a mixed mode controlled oscillator. The circuit comprises a charge pump, and a digital loop filter. The charge pump is coupled to the mixed mode controlled oscillator. The charge pump receives an up/down signal and sends a current signal to the mixed mode controlled oscillator. The digital loop filter receives the up/down signal and generates a digital code signal to the mixed mode controlled oscillator. An output frequency of the mixed mode controlled oscillator is controlled by the current signal and the digital code signal.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: February 10, 2015
    Assignee: MediaTek Inc.
    Inventors: Ping-Ying Wang, Kuan-Hua Chao, Jeng-Horng Tsai
  • Patent number: 8896386
    Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 25, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wen-Chang Lee, Ping-Ying Wang
  • Publication number: 20140240053
    Abstract: A digitally controlled oscillator includes a ring oscillator and a first supplementary circuit. The ring oscillator is coupled to a supply voltage and generates a signal oscillated at an oscillating frequency. The oscillating frequency is controlled by a digital code and further varies with a supply voltage drift in a first direction. The first supplementary circuit is coupled to the ring oscillator and facilitates the oscillating frequency to vary with the supply voltage drift in a second direction reverse to the first direction.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: MediaTek Inc.
    Inventors: Yi-Chieh HUANG, Ping-Ying WANG
  • Patent number: 8660209
    Abstract: A transmitter is provided. The transmitter includes a phase/frequency deviation input, a controller and a frequency modulating path. The phase/frequency deviation input receives multiple phase/frequency deviation samples. The controller outputs a modified phase/frequency deviation signal and generates a phase/frequency deviation carry-out signal in response to the phase/frequency deviation samples and a previous time sample of the phase/frequency deviation carry-out signal. The frequency modulating path performs frequency modulation in response to the modified phase/frequency deviation signal and outputs a frequency modulated carrier signal.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: February 25, 2014
    Assignee: Mediatek Inc.
    Inventors: Kai-Peng Kao, Chi-Hsueh Wang, Robert Bogdan Staszewski, Ping-Ying Wang
  • Patent number: 8644441
    Abstract: Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: February 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Bo-Jiun Chen, Shang-Ping Chen, Ping-Ying Wang
  • Publication number: 20130234800
    Abstract: A calibration device arranged for calibrating an oscillating frequency of an oscillator includes: a phase locking device arranged to track a first reference clock generated by the oscillator until a feedback clock is phase-aligned with the first reference clock, and then arranged to track a second reference clock generated by the oscillator until a phase difference between the second reference clock and the feedback clock is a static phase difference, wherein the feedback clock is generated by dividing an output oscillating signal of the phase locking device by a divisor; an adjusting circuit arranged to adjust the divisor into an updated divisor to reduce the static phase difference between the second reference clock and the feedback clock; and a calibrating circuit arranged to calibrate the oscillating frequency of the oscillator according to the updated divisor, wherein the second reference clock is generated by varying a control signal of the oscillator.
    Type: Application
    Filed: March 6, 2013
    Publication date: September 12, 2013
    Applicant: MEDIATEK SINGAPORE PTE. LTD.
    Inventors: Wen-Chang Lee, Ping-Ying Wang
  • Patent number: 8531214
    Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: September 10, 2013
    Assignee: MediaTek Inc.
    Inventors: Shang-Ping Chen, Ping-Ying Wang
  • Patent number: 8525713
    Abstract: A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: September 3, 2013
    Inventor: Ping-Ying Wang
  • Patent number: 8502613
    Abstract: An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: August 6, 2013
    Assignee: Mediatek Inc.
    Inventors: Ping-Ying Wang, Hsiang-Hui Chang
  • Publication number: 20130188754
    Abstract: A transmitter is provided. The transmitter includes a phase/frequency deviation input, a controller and a frequency modulating path. The phase/frequency deviation input receives multiple phase/frequency deviation samples. The controller outputs a modified phase/frequency deviation signal and generates a phase/frequency deviation carry-out signal in response to the phase/frequency deviation samples and a previous time sample of the phase/frequency deviation carry-out signal. The frequency modulating path performs frequency modulation in response to the modified phase/frequency deviation signal and outputs a frequency modulated carrier signal.
    Type: Application
    Filed: September 13, 2012
    Publication date: July 25, 2013
    Applicant: MEDIATEK INC.
    Inventors: Kai-Peng Kao, Chi-Hsueh Wang, Robert Bogdan Staszewski, Ping-Ying Wang
  • Patent number: 8436761
    Abstract: An analog-to-digital converter including a comparator, a control module, a voltage adjusting module, and an evaluating module is provided. The comparator compares an analog input voltage with a feedback voltage and generates a comparison result. Based on the comparison result, the control module generates a control signal. The voltage adjusting module increases or decreases the feedback voltage toward the analog input voltage according to the control signal. The voltage increase amount and decrease amount provided by the voltage adjusting module are corresponding to a first digital value and a second digital value, respectively. The evaluating module generates the first digital value and the second digital value based on the control signal. According to the first digital value and the second digital value, a digital signal corresponding to the analog input voltage is generated.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: May 7, 2013
    Inventor: Ping-Ying Wang
  • Patent number: 8379787
    Abstract: Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: February 19, 2013
    Assignee: Mediatek Inc.
    Inventors: Shang-Ping Chen, Ping-Ying Wang
  • Patent number: 8368480
    Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: February 5, 2013
    Assignee: Mediatek Inc.
    Inventor: Ping-Ying Wang