Abstract: A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component.

Abstract: A voltage converter for converting an analog input signal into a digital signal is provided. The pulse width of the digital signal is relative to the voltage level of the analog input signal. The voltage converter includes a comparator and a feedback module. After comparing the analog input signal and an analog feedback signal, the comparator generates the digital signal. When the analog input signal is higher than the analog feedback signal, the digital signal has a first voltage level. When the analog input signal is lower than the analog feedback signal, the digital signal has a second voltage level, which is different from the first voltage level. Based on the digital signal, the feedback module adjusts the analog feedback signal toward the analog input signal.

Abstract: A digital-intensive signal processor including a signal converting module and a feedback module in a closed timing loop. The signal converting module converts a control signal to an output signal with phase/frequency related to the control signal. The feedback module detects the phase difference between a reference signal and a feedback signal and generates an original control signal based on the phase difference, so as to keep the phases of the output signal and the reference signal related. The feedback signal is associated with the output signal. The control signal includes the original control signal and a signal to be processed. The phase difference, original control signal, control signal, or output signal is a processed signal corresponding to the signal to be processed.

Abstract: A timing adjusting circuit including a time amplifier and a phase adjusting module is provided. The time amplifier is used for increasing the active pulse-width of a phase control signal, so as to generate an adjusted control signal. Based on the adjusted control signal, the phase adjusting module adjusts the phase of an output signal. The phase of the output signal is associated with the active pulse-width of the phase control signal.

Abstract: An analog-to-digital converter including a comparator, a control module, a voltage adjusting module, and an evaluating module is provided. The comparator compares an analog input voltage with a feedback voltage and generates a comparison result. Based on the comparison result, the control module generates a control signal. The voltage adjusting module increases or decreases the feedback voltage toward the analog input voltage according to the control signal. The voltage increase amount and decrease amount provided by the voltage adjusting module are corresponding to a first digital value and a second digital value, respectively. The evaluating module generates the first digital value and the second digital value based on the control signal. According to the first digital value and the second digital value, a digital signal corresponding to the analog input voltage is generated.

Abstract: A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period control word and generates a phase selection signal. The delay line unit generates an output clock based on the phase selection signal. The delta-sigma modulator performs a carry-in operation based on a base number and the base number is adjustable and determined by a calibration process of the delay line unit.

Abstract: Phase locked loop circuits capable of increasing an equivalent capacitance thereof to improve stability are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a control signal according to the phase error signal, a controllable oscillator providing an output clock according to the control signal, and a sampling adjustment unit decreasing the number of times the control signal is updated according to the phase error signal. A proportional part is coupled between the controllable oscillator and a reference clock and operated in a fraction mode.

Abstract: An oscillating circuit including a digital sigma-delta modulator and a controlled oscillator is disclosed. The digital sigma-delta modulator receives a fractional bit signal to generate a control signal. The controlled oscillator includes a varactor dynamically coupled to receive the control signal.

Abstract: A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

Abstract: A phase locked loop (PLL) with a loop bandwidth calibration circuit is provided. The mixed-mode PLL comprises an analog phase correction path, a digital frequency correction path, a calibration current source, and a loop bandwidth calibration circuit. The analog phase correction path comprises a linear phase correction unit (LPCU). The digital frequency correction path comprises a digital integral path circuit. The calibration current source is coupled to the LPCU. The loop bandwidth calibration circuit is coupled to a frequency divider and coupled between the input and output of the PLL. The loop bandwidth calibration circuit operates after the calibration current source injects a calibration current into the LPCU.

Abstract: A signal processing circuit includes: a phase modulating path arranged to adjust a phase component of an input signal to generate an adjusted phase component such that a phase difference of the input signal falls within a target phase difference range; and an amplitude modulating path arranged to exchange a sign of an amplitude component of the input signal corresponding to the phase component to generate an adjusted amplitude component when the phase modulating path adjusts the phase component.

Abstract: A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.

Abstract: A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component.

Abstract: A phase-locked loop circuit. The phase-locked loop circuit comprises a phase detector, a proportional charge pump, a decimator, an integral charge pimp, and a voltage-controlled oscillator. The phase detector obtains an phase error information according to a phase difference between a reference signal and a clock signal input to the phase detector. The proportional charge pump coupled to the phase detector generates a first voltage according to the phase error information. The decimator generates a decimated version of the phase error information by a decimation factor of N. The integral charge pump generates a second voltage according to the decimated version of the phase error information. The voltage-controlled oscillator generating the clock signal according to a combination of the first and second voltages.

Abstract: A charge pump-based frequency modulator is provided. The charge pump-based frequency modulator comprises an analog phase correction path comprising a varactor and a charge pump. The varactor is coupled to an output of the charge pump-based frequency modulator. The charge pump is coupled to a node between the varactor and the output and receives a signal containing the modulated data.

Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.

Abstract: Phase locked loop circuits capable of increasing an equivalent capacitance thereof to improve stability are provided, in which an integral part comprises a first phase frequency detector providing a phase error signal, a first charge pump circuit generating a control signal according to the phase error signal, a controllable oscillator providing an output clock according to the control signal, and a sampling adjustment unit decreasing the number of times the control signal is updated according to the phase error signal. A proportional part is coupled between the controllable oscillator and a reference clock and operated in a fraction mode.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.