Patents by Inventor Pinping Sun
Pinping Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170358691Abstract: Various particular embodiments include a semiconductor varactor structure including: a semiconductor substrate of a first conductivity type; a semiconductor area of a second conductivity type, different from the first conductivity type, within the semiconductor substrate; a field effect transistor (FET) structure within the semiconductor area; and a contact, contacting the semiconductor area, for applying a voltage bias to the semiconductor area.Type: ApplicationFiled: June 14, 2016Publication date: December 14, 2017Inventors: Kai Xiu, Chengwen Pei, Pinping Sun
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Patent number: 9741485Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure.Type: GrantFiled: August 11, 2015Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Pinping Sun, Chengwen Pei, Zheng Xu
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Patent number: 9240406Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: GrantFiled: April 21, 2014Date of Patent: January 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Patent number: 9218903Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure.Type: GrantFiled: September 26, 2013Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Pinping Sun, Chengwen Pei, Zheng Xu
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Publication number: 20150348919Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure.Type: ApplicationFiled: August 11, 2015Publication date: December 3, 2015Inventors: Pinping Sun, Chengwen Pei, Zheng Xu
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Publication number: 20150303191Abstract: A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.Type: ApplicationFiled: April 21, 2014Publication date: October 22, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Dan Moy, Chengwen Pei, Robert R. Robison, Pinping Sun, Richard A. Wachnik, Ping-Chuan Wang
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Patent number: 9093453Abstract: An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow.Type: GrantFiled: October 7, 2013Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
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Publication number: 20150145710Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: ApplicationFiled: November 26, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, WILLIAM R. KELLY, JOSEPH F. LOGAN, PINPING SUN
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Patent number: 9041572Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: GrantFiled: November 26, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Matthew B. Baecher, William R. Kelly, Joseph F. Logan, Pinping Sun
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Patent number: 9035708Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.Type: GrantFiled: June 13, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventor: Pinping Sun
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Patent number: 9024411Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.Type: GrantFiled: August 12, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
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Publication number: 20150097266Abstract: An electronic fuse link with lower programming current for high performance and self-aligned methods of forming the same. The invention provides a horizontal e-fuse structure in the middle of the line. A reduced fuse link width is achieved by spacers on sides of pair of dummy or active gates, to create sub-lithographic dimension between gates with spacers to confine a fuse link. A reduced height in the third dimension on the fuse link achieved by etching the link, thereby creating a fuse link having a sub-lithographic size in all dimensions. The fuse link is formed over an isolation region to enhanced heating and aid fuse blow.Type: ApplicationFiled: October 7, 2013Publication date: April 9, 2015Applicant: International Business Machines CorporationInventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
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Publication number: 20150084733Abstract: A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure.Type: ApplicationFiled: September 26, 2013Publication date: March 26, 2015Applicant: International Business Machines CorporationInventors: Pinping Sun, Chengwen Pei, Zheng Xu
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Publication number: 20150041950Abstract: A three-dimensionally (3d) confined conductor advantageously used as an electronic fuse and self-aligned methods of forming the same. By non-conformal deposition of a dielectric film over raised structures, a 3d confined tube, which may be sub-lithographic, is formed between the raised structures. Etching holes which intersect the 3d confined region and subsequent metal deposition fills the 3d confined region and forms contacts. When the raised structures are gates, the fuse element may be located at the middle of the line (i.e. in pre-metal dielectric). Other methods for creating the structure are also described.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: International Business Machines CorporationInventors: Junjun Li, Yan Zun Li, Chengwen Pei, Pinping Sun
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Publication number: 20140368286Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) circuit is provided, in which a parallel connection of a capacitor and a resistor configured to provide frequency-dependent transconductance is present across source nodes of a first pair of field effect transistors in which gate nodes and drain nodes are cross-coupled. The source nodes of the first pair of field effect transistors are electrically shorted to drain nodes of a second pair of field effect transistors of which the gate nodes are electrically shorted to the gate nodes of the first pair of field effect transistors. The parallel connection of the capacitor and the resistor includes a parallel connection of a capacitor and a resistor such that the net transconductance of the first pair of field effect transistors is less at low frequencies where thermal noise and flicker noise are dominant part of the phase noise than at the operational frequency range.Type: ApplicationFiled: June 13, 2013Publication date: December 18, 2014Inventor: Pinping Sun
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Patent number: 8779870Abstract: A low phase variation attenuator uses a combined attenuation path and a phase network to significantly reduce a phase error between a reference signal and an attenuated signal without degrading the insertion loss. A grounded parallel connection of a resistor and a capacitor is employed in series with an attenuation transistor, which is connected to a middle of a two resistor voltage divider. The two resistor voltage divider includes two resistors of equal resistance that are connected in a series connection. The two resistor voltage divider is connected in a parallel connection with a reference transistor, which functions as a main switch for the transmission or attenuation of a radio frequency (RF) signal.Type: GrantFiled: October 5, 2011Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Pinping Sun, Hanyi Ding, Wayne H. Woods, Jr.
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Patent number: 8766735Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) is provided, in which the body of each transistor within a pair of cross-coupled transistors is coupled to the gate of the same transistor through a resistor. The body transconductance is employed to enhance the negative resistance of the cross-coupled pair of transistors. At the same time, a forward body bias voltage reduces the threshold voltage of the cross-coupled pair to allow the VCO to operate at a low power supply voltage. Further, the resistor connected between the body and the drain of each transistor voids the leakage in the substrate, and thus, reduces power consumption of the VCO further. This VCO provides low power operation with enhanced figure of merit without employing any extra inductors besides the inductors that are part of the LC tank.Type: GrantFiled: November 20, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Pinping Sun, Chengwen Pei
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Publication number: 20140139295Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) is provided, in which the body of each transistor within a pair of cross-coupled transistors is coupled to the gate of the same transistor through a resistor. The body transconductance is employed to enhance the negative resistance of the cross-coupled pair of transistors. At the same time, a forward body bias voltage reduces the threshold voltage of the cross-coupled pair to allow the VCO to operate at a low power supply voltage. Further, the resistor connected between the body and the drain of each transistor voids the leakage in the substrate, and thus, reduces power consumption of the VCO further. This VCO provides low power operation with enhanced figure of merit without employing any extra inductors besides the inductors that are part of the LC tank.Type: ApplicationFiled: November 20, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: Pinping Sun, Chengwen Pei
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Patent number: 8643191Abstract: Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.Type: GrantFiled: January 26, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Hanyi Ding, Pinping Sun, Guoan Wang, Wayne H. Woods, Jr.
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Patent number: 8514028Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance.Type: GrantFiled: August 17, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Pinping Sun, Hailing Wang