Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: An integrated circuit includes a first plurality of circuits receiving a first internal power supply voltage, a first regulator receiving an external power supply voltage and supplying the first internal power supply voltage at a first rated power in response to the external power supply voltage when the integrated circuit is in an active mode, a second regulator receiving the external power supply voltage for supplying the first internal power supply voltage at a second rated power less than said first rated power in response to the external power supply voltage when the integrated circuit is in a low power mode, and a controller controlling a transition of the integrated circuit between the active mode and the low power mode. The controller activates all of the first plurality of circuits in the active mode, but only a subset of them while keeping remaining ones inactive in the low power mode.

Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: In one embodiment, an apparatus includes: a bias circuit having a replica circuit, the bias circuit to generate an oscillator current that is proportional to a variation of the replica circuit; an oscillator circuit coupled to the bias circuit to receive the oscillator current and generate a plurality of signals using the oscillator current; and a waveform shaper circuit coupled to the oscillator circuit to receive the plurality of signals and generate at least one clock signal from the plurality of signals.

Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

Abstract: A low power wake on radio circuit detects if an RF signal is present on an input to the wake on radio circuit. An RF sense circuit supplies an RF sense signal indicating whether the RF signal is present on the input. The RF sense signal is used to incrementally turn on digital decode logic to determine if a radio transmission that is unique to the wake on radio circuit has been received. If the unique radio transmission have been received, the wake on radio circuit supplies a wakeup signal to the rest of the system.

Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

Abstract: In an embodiment, an integrated circuit includes: a voltage regulator to receive a first voltage and regulate the first voltage to output a regulated voltage; a first logic circuit to operate using the regulated voltage; and a regulator control circuit to receive a control signal during a boot of the integrated circuit via a general purpose pad of the integrated circuit and control the voltage regulator to operate in one of an enabled mode and a bypass mode based at least in part on the control signal.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.

Abstract: Techniques relating to buffer circuits. In one embodiment, a circuit includes a first transistor configured as a source follower and a feed-forward path coupled to the gate terminal of the first transistor and the drain terminal of the first transistor. In this embodiment, the feed-forward path includes circuitry configured to decouple the feed-forward path from a DC component of an input signal to the gate terminal of the first transistor. In this embodiment, the circuitry is configured to reduce a drain-source voltage of the first transistor based on the input signal. In some embodiment, the feed-forward path includes a second transistor configured as a source follower and the source terminal of the second transistor is coupled to the drain terminal of the first transistor. In various embodiments, reducing the drain-source voltage may improve linearity of the first transistor.

Abstract: An amplifier includes a negative gain amplifier, a load element, and a transconductance device. The negative gain amplifier has an input and an output. The load element has a first terminal coupled to a power supply voltage terminal, and a second terminal. The transconductance device has a first current electrode coupled to the second terminal of the load element, a control electrode coupled to the output of the negative gain amplifier, and a second current electrode coupled to the input of the negative gain amplifier.

Abstract: Externally configurable power-on-reset systems and methods for integrated circuits are disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide operational configurations determined by external connections. In one configuration where no dedicated external reset signal is desired, the reset control circuitry relies upon the internal power-one-reset circuitry to generate the internal reset control signal. In another configuration where an external reset signal is utilized, the reset control circuitry relies upon the external reset signal, which overrides the internal power-on-reset circuitry, to generate the internal reset control signal. In further configurations, the reset control circuitry utilizes logic circuitry controlled through a digital interface to determine when the internal reset control signal can be de-asserted.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: An integrated circuit (IC) having a radio receiver configured to perform a jitter self-test is disclosed. In one embodiment, an IC includes a radio receiver and a pulse generator. The pulse generator is configured to generate a pulse train based on a first periodic signal received from the radio receiver. The radio receiver is configured to use the pulse train to determine an amount of phase noise generated by a local oscillator of the radio receiver. The pulse generator and the radio receiver are implemented on the same IC die.

Abstract: In one embodiment, an internal buffer may be provided within an integrated circuit (IC) to convert a signal to an output current to be output via a pin of the IC, under control of a switch which can be controlled based on a configuration setting of the IC, and may selectively directly couple the signal to the pin when the IC is coupled to an external driver circuit.

Abstract: Externally configurable power-on-reset systems and methods for integrated circuits are disclosed that utilize internal power-on-reset circuitry and reset control circuitry to provide operational configurations determined by external connections. In one configuration where no dedicated external reset signal is desired, the reset control circuitry relies upon the internal power-one-reset circuitry to generate the internal reset control signal. In another configuration where an external reset signal is utilized, the reset control circuitry relies upon the external reset signal, which overrides the internal power-on-reset circuitry, to generate the internal reset control signal. In further configurations, the reset control circuitry utilizes logic circuitry controlled through a digital interface to determine when the internal reset control signal can be de-asserted.