Abstract: An integrated circuit (IC) having a radio receiver configured to perform a jitter self-test is disclosed. In one embodiment, an IC includes a radio receiver and a pulse generator. The pulse generator is configured to generate a pulse train based on a first periodic signal received from the radio receiver. The radio receiver is configured to use the pulse train to determine an amount of phase noise generated by a local oscillator of the radio receiver. The pulse generator and the radio receiver are implemented on the same IC die.

Abstract: Techniques are disclosed relating to tracking edges of a signal of a buffer circuit. In one embodiment, an apparatus is disclosed that includes a sampling circuit configured to sample a pulse width modulation (PWM) signal to generate a threshold voltage based on an average of the high and low voltage levels of the PWM signal and to provide the threshold voltage to an input of a comparator of the apparatus. The comparator is configured receive the threshold voltage and the PWM voltage and perform edge detection on the threshold voltage and PWM signal.

Abstract: A voltage-to-current converter includes a transconductance stage including an input configured to receive a scaled voltage signal, a first output to carry a first current based on the scaled voltage signal, and a second output to carry a second current that is proportional to the first current. The voltage-to-current converter further includes a digital feedback loop coupled to the second output of the transconductance stage and configured to adjust the scaled voltage signal based on an error between an external reference voltage and a sense voltage derived from the second current to compensate for changes in the scaled voltage signal.

Abstract: A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step.

Abstract: A fractional-N divider receives an input signal and supplies a divided signal divided in accordance with an integer divide control signal determined from a divide ratio. A phase interpolator is coupled to the fractional-N divider to adjust a phase of the divided signal according to a fractional portion of the divide ratio. The apparatus, responsive to a request for a frequency adjustment of the generated signal in a programmable number of steps, is configured to adjust the frequency of the generated signal from a beginning frequency to an ending frequency in the programmable number of steps by adjusting the supplied divide ratio at each step.