Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Abstract: Performance of an electrohydrodynamic fluid accelerator device may be improved and adverse events such as sparking or arcing may be reduced based, amongst other things, on electrode geometries and/or positional interrelationships of the electrodes. For example, in a class of EHD devices that employ a longitudinally elongated corona discharge electrode (often, but not necessarily, a wire), a plurality of generally planar, collector electrodes may be positioned so as to present respective leading surfaces toward the corona discharge electrode. The generally planar collector electrodes may be oriented so that their major surfaces are generally orthogonal to the longitudinal extent of the corona discharge electrode. In such EHD devices, a high intensity electric field can be established in the “gap” between the corona discharge electrode and leading surfaces of the collector electrodes.

Abstract: In thermal management systems that employ EHD devices to motivate flow of air between ventilated boundary portions of an enclosure, it can be desirable to have some heat transfer surfaces participate in electrohydrodynamic acceleration of fluid flow while providing additional heat transfer surfaces that may not. In some embodiments, both collector electrodes and additional heat transfer surfaces are thermally coupled into a heat transfer path. Collector electrodes then contribute both to flow of cooling air and to heat transfer to the air flow so motivated. The collector electrodes and additional heat transfer surfaces may be parts of a unitary, or thermally coupled, structure that is introduced into a flow path at multiple positions therealong. In some embodiments, the collector electrodes and additional heat transfer surfaces may be proximate each other along the flow path. In some embodiments, the collector electrodes and additional heat transfer surfaces may be separate structures.

Abstract: Reversible flow may be provided in certain EHD device configurations that selectively energize corona discharge electrodes arranged to motivate flows in generally opposing directions. In some embodiments, a first set of one or more corona discharge electrodes is positioned, relative to a first array of collector electrode surfaces, to when energized, motivate flow in a first direction, while second set of one or more corona discharge electrodes is positioned, relative to a second array of collector electrode surfaces, to when energized, motivate flow in a second direction that opposes the first. In some embodiments, the first and second arrays of collector electrode surfaces are opposing surfaces of individual collector electrodes. In some embodiments, the first and second arrays of collector electrode surfaces are opposing surfaces of respective collector electrodes.

Abstract: Barrier layers for use in electrical applications. In some embodiments the barrier layer is a laminated barrier layer. In some embodiments the barrier layer includes a graded barrier layer.

Abstract: A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure.

Abstract: A microelectronic assembly can include first, second and third stacked substantially planar elements, e.g., of dielectric or semiconductor material, and which may have a CTE of less than 10 ppm/° C. The assembly may be a microelectronic package and may incorporate active semiconductor devices in one, two or more of the first, second or third elements to function cooperatively as a system-in-a-package. In one example, an electrically conductive element having a minimum thickness less than 10 microns, may be formed by plating, and may electrically connect two or more of the first, second or third elements. The conductive element may entirely underlie a surface of another one of the substantially planar elements.

Abstract: A microelectronic assembly can include a substrate having first and second surfaces, at least two logic chips overlying the first surface, and a memory chip having a front surface with contacts thereon, the front surface of the memory chip confronting a rear surface of each logic chip. The substrate can have conductive structure thereon and terminals exposed at the second surface for connection with a component. Signal contacts of each logic chip can be directly electrically connected to signal contacts of the other logic chips through the conductive structure of the substrate for transfer of signals between the logic chips. The logic chips can be adapted to simultaneously execute a set of instructions of a given thread of a process. The contacts of the memory chip can be directly electrically connected to the signal contacts of at least one of the logic chips through the conductive structure of the substrate.

Abstract: A microelectronic unit can include a substrate having front and rear surfaces and active semiconductor devices therein, the substrate having a plurality of openings arranged in a symmetric or asymmetric distribution across an area of the rear surface, first and second conductive vias connected to first and second pads exposed at the front surface, pluralities of first and second conductive interconnects extending within respective ones of the openings, and first and second conductive contacts exposed for interconnection with an external element. The plurality of first conductive interconnects can be separated from the plurality of second conductive interconnects by at least one of the plurality of openings, the at least one opening at least partially filled with an insulating material. The distribution of the openings can include at least m openings spaced apart in a first direction and n openings spaced apart in a second direction transverse to the first direction.

Abstract: A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a semiconductor region adjacent a rear face. The semiconductor region has a first region of material overlying the first light sensing element and a second region of material overlying the second light sensing element such that the first and second wavelengths are able to pass through the first and second regions, respectively, and reach the first and second light sensing elements with substantially the same intensity.

Abstract: A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face such that the first and second light sensing elements receive light of substantially the same intensity. A dielectric region is provided at least substantially filling a space of the semiconductor region adjacent at least one of the light sensing elements. The dielectric region may include at least one light guide.

Abstract: A microelectronic image sensor assembly for backside illumination and method of making same are provided. The assembly includes a microelectronic element having contacts exposed at a front face and light sensing elements arranged to receive light of different wavelengths through a rear face. A semiconductor region has an opening overlying at least one of first and second light sensing elements, the semiconductor region having a first thickness between the first light sensing element and the rear face and a second thickness between the second light sensing element and the rear face. A light-absorbing material overlies the semiconductor region within the opening above at least one of the light sensing elements such that the first and second light sensing elements receive light of substantially the same intensity.

Abstract: A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape.

Abstract: A method of bonding a first substrate and a second substrate includes the steps of rotating first substrate with an adhesive mass thereon, and second substrate contacting the mass and overlying the first substrate, controlling a vertical height of a heated control platen spaced apart from and not contacting the second substrate so as to control a temperature of the adhesive mass, so as to at least one of bond the first and second substrates in alignment with one another, or achieve a sufficiently planar adhesive interface between the first and second substrates.

Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Abstract: A method of bonding first and second microelectronic elements includes pressing together a first substrate containing active circuit elements therein with a second substrate, with a flowable dielectric material between confronting surfaces of the respective substrates, each of the first and second substrates having a coefficient of thermal expansion less than 10 parts per million/° C., at least one of the confronting surfaces having a plurality of channels extending from an edge of such surface, such that the dielectric material between planes defined by the confronting surfaces is at least substantially free of voids and has a thickness over one micron, and at least some of the dielectric material flows into at least some of the channels.

Abstract: A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Abstract: A component includes a substrate and a capacitor formed in contact with the substrate. The substrate can consist essentially of a material having a coefficient of thermal expansion of less than 10 ppm/° C. The substrate can have a surface and an opening extending downwardly therefrom. The capacitor can include at least first and second pairs of electrically conductive plates and first and second electrodes. The first and second pairs of plates can be connectable with respective first and second electric potentials. The first and second pairs of plates can extend along an inner surface of the opening, each of the plates being separated from at least one adjacent plate by a dielectric layer. The first and second electrodes can be exposed at the surface of the substrate and can be coupled to the respective first and second pairs of plates.

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.