Abstract: A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross- sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor is formed. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is conformally formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: A method of forming a metal silicide layer includes the following steps. At first, at least a gate structure, at least a source/drain region and a first dielectric layer are formed on a substrate, and the gate structure is aligned with the first dielectric layer. Subsequently, a cap layer covering the gate structure is formed, and the cap layer does not overlap the first dielectric layer and the source/drain region. Afterwards, the first dielectric layer is removed to expose the source/drain region, and a metal silicide layer totally covering the source/drain region is formed.

Abstract: A plug structure including a first dielectric layer, a second dielectric layer, a barrier layer and a second plug is provided. The first dielectric layer having a first plug therein is located on a substrate, wherein the first plug physically contacts a source/drain in the substrate. The second dielectric layer having an opening exposing the first plug is located on the first dielectric layer. The barrier layer conformally covers the opening, wherein the barrier layer has a bottom part and a sidewall part, and the bottom part is a single layer and physically contacts the first plug while the sidewall part is a dual layer. The second plug fills the opening and on the barrier layer. Moreover, a process of forming a plug structure is also provided.

Abstract: A manufacturing method of semiconductor devices having metal gate includes following steps. A substrate having a first semiconductor device and a second semiconductor device formed thereon is provided. The first semiconductor device includes a first gate trench and the second semiconductor device includes a second gate trench. A first work function metal layer is formed in the first gate trench and the second gate trench. A portion of the first work function metal layer is removed from the second gate trench. A second work function metal layer is formed in the first gate trench and the second gate trench. The second work function metal layer and the first work function metal layer include the same metal material. A third work function metal layer and a gap-filling metal layer are sequentially formed in the first gate trench and the second gate trench.

Abstract: An embedded resistor including a first interdielectric layer, a cap layer, a resistive layer and a cap film is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The resistive layer conformally covers the trench, thereby having a U-shaped cross-sectional profile. The cap film is located in the trench and on the resistive layer, or, an embedded thin film resistor including a first interdielectric layer, a cap layer and a bulk resistive layer is provided. The first interdielectric layer is located on a substrate. The cap layer is located on the first interdielectric layer, wherein the cap layer has a trench. The bulk resistive layer is located in the trench.

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract: A static random access memory unit cell layout structure is disclosed, in which a slot contact is disposed on one active area and another one across from the one. A static random access memory unit cell structure and a method of fabricating the same are also disclosed, in which, a slot contact is disposed on drains of a pull-up transistor and a pull-down transistor, and a metal-zero interconnect is disposed on the slot contact and a gate line of another pull-up transistor. Accordingly, there is not an intersection of vertical and horizontal metal-zero interconnects, and there is no place suffering from twice etching. Leakage junction due to stitch recess can be avoided.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.

Abstract: An epitaxial process includes the following steps. A substrate including a first area and a second area is provided. A first gate and a second gate are formed respectively on the substrate of the first area and the second area. A first spacer and a second spacer are respectively formed on the substrate beside the first gate and the second gate at the same time. A first epitaxial structure is formed beside the first spacer and then a second epitaxial structure is formed beside the second spacer by the first spacer and the second spacer respectively.

Abstract: A method for forming a semiconductor device comprises the following steps: first, a substrate is provided, a first photo-etching process is carried out with a first photomask to form at least one device structure and a plurality of compensation structures, wherein the first photomask comprises at least one device pattern and a plurality of dummy patterns. A photoresist layer is then formed on the device structure and each compensation structures; a second photo-etching process is then carried out with a second photomask to remove each compensation structure.

Abstract: A method of forming a semiconductor structure having at least a contact plug includes the following steps. At first, at least a transistor and an inter-layer dielectric (ILD) layer are formed on a substrate, and the transistor includes a gate structure and two source/drain regions. Subsequently, a cap layer is formed on the ILD layer and on the transistor, and a plurality of openings that penetrate through the cap layer and the ILD layer until reaching the source/drain regions are formed. Afterward, a conductive layer is formed to cover the cap layer and fill the openings, and a part of the conductive layer is further removed for forming a plurality of first contact plugs, wherein a top surface of a remaining conductive layer and a top surface of a remaining cap layer are coplanar, and the remaining cap layer totally covers a top surface of the gate structure.

Abstract: A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled.

Abstract: A semiconductor structure includes a first gate and a second gate, a first spacer and a second spacer, two first epitaxial structures and two second epitaxial structures. The first gate and the second gate are located on a substrate. The first spacer and the second spacer are respectively located on the substrate beside the first gate and the second gate. The first epitaxial structures and the second epitaxial structures are respectively located in the substrate beside the first spacer and the second spacer, wherein the first spacer and the second spacer have different thicknesses, and the spacing between the first epitaxial structures is different from the spacing between the second epitaxial structures. Moreover, the present invention also provides a semiconductor process forming said semiconductor structure.

Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.

Abstract: The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.

Abstract: The present invention provides a semiconductor structure including at least a contact plug. The structure includes a substrate, a transistor, a first ILD layer, a second ILD layer and a first contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor and levels with a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The first contact plug is disposed in the first ILD layer and the second ILD layer and includes a first trench portion and a first via portion, wherein a boundary of the first trench portion and a first via portion is higher than the top surface of the gate. The present invention further provides a method of making the same.

Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Abstract: The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.