Patents by Inventor Po-Chun Chen

Po-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811272
    Abstract: A method of forming a dielectric layer includes the following steps. A substrate including a first area and a second area is provided. A plurality of patterns on the substrate of the first area and a blanket stacked structure on the substrate of the second area are formed. An organic dielectric layer covers the patterns, the blanket stacked structure and the substrate. The blanket stacked structure is patterned by serving the organic dielectric layer as a hard mask layer, thereby forming a plurality of stacked structures. The organic dielectric layer is removed. A dielectric layer blanketly covers the patterns, the stacked structures, and the substrate.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 20, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsin Liu, Ta-Wei Chiu, Chia-Lung Chang, Po-Chun Chen, Hong-Yi Fang, Yi-Wei Chen
  • Publication number: 20200326755
    Abstract: A shockproof element is applied to an electronic element. The shockproof element includes a first elastic portion, a second elastic portion and a connecting portion. The first elastic portion defines an opening. The second elastic portion is disposed corresponding to the first elastic portion. The second elastic portion includes a hollow column. The hollow column extends from the second elastic portion into the opening of the first elastic portion. The hollow column can fix the electronic element, and the first elastic portion and the second elastic portion jointly hold the electronic element. The connecting portion connects to the first elastic portion and the second elastic portion. An electronic device, which includes the shockproof element, the electronic element, a first housing and a second housing, is also provided.
    Type: Application
    Filed: April 9, 2020
    Publication date: October 15, 2020
    Inventors: Chiao-Yi LIN, Po-Chun CHEN
  • Publication number: 20200328210
    Abstract: An integrated circuit includes a first transistor, a second transistor, and a first insulating layer. The first transistor is disposed in a first layer and comprises a first gate. The second transistor is disposed in a second layer above the first layer and comprises a second gate. The first gate and second gate are separated from each other in a first direction. The first insulating layer is disposed between the first gate of the first transistor and the second gate of the second transistor. The first insulating layer is configured to electrically insulate the first gate of the first transistor from the second gate of the second transistor.
    Type: Application
    Filed: March 2, 2020
    Publication date: October 15, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei WU, Po-Chun WANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Li-Chun TIEN
  • Patent number: 10804101
    Abstract: A semiconductor structure including a substrate and a nucleation layer over the substrate. The semiconductor structure further includes a first III-V layer over the nucleation layer, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes one or more sets of III-V layers over the first III-V layer. Each set of the one or more sets of III-V layers includes a lower III-V layer, wherein the lower III-V layer has a second dopant type opposite the first dopant type, and an upper III-V layer on the lower III-V layer, wherein the upper III-V layer has the first dopant type. The semiconductor structure further includes a second III-V layer over the one or more sets of III-V layers, the second III-V layer having the second dopant type.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200323028
    Abstract: A method of enhancing IP packet forwarding feature support after interworking is proposed. When a PDU session in 5GS is transferred to a PDN connection in EPS, the UE shall assume the feature is supported after inter-system change from 5GS to EPS. When a PDN connection is established in EPS, the network indicated that the feature is not supported, and the network provided 5GSM parameters for ESM/5GSM interworking for this PDN connection, then UE shall assume the feature is supported after inter-system change from EPS to 5GS, the UE shall also assume the feature is supported after inter-system change from 5GS back to EPS. The IP packet forwarding features include PS data off and local IP address in TFT.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Inventors: Chien-Chun Huang-Fu, Chi-Hsien Chen, Po-Ying Chuang, Po Kuang Lu
  • Patent number: 10796060
    Abstract: A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Li-Chun Tien, Shun-Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang
  • Publication number: 20200308481
    Abstract: A contact lens includes at least one color changeable region, wherein the color changeable region includes at least one photoluminescence material. When a wavelength of the photoluminescence material having a maximum radiation intensity is WEmMx, an average transmittance in a wavelength range of 400 nm-700 nm of the color changeable region is T4070, a size of a total area of the color changeable region is AC, and a size of a total area of the contact lens is AL, certain conditions relating to WEmMx, T4070 and AC/AL are satisfied.
    Type: Application
    Filed: February 19, 2020
    Publication date: October 1, 2020
    Inventors: Wei-Yuan CHEN, Po-Tsun CHEN, Wei-Chun CHEN, Chun-Hung TENG
  • Patent number: 10790289
    Abstract: A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Po-Chun Chen, Chia-Lung Chang
  • Patent number: 10780504
    Abstract: A powder recycling system includes a supply tank, a continuous loss-in-weight module, a pneumatic module, a transfer channel, a recycle module, and a refilling tank. The supply tank accommodates recycling powder. The continuous loss-in-weight module includes a storage tank receiving the recycling powder from the supply tank and a rotary output pipe connected to the storage tank to output the recycling powder. The continuous loss-in-weight module controls the mass flow rate of the output of the recycling powder according to the weight change of the storage tank. The pneumatic module enables the recycling powder to float and move in the transfer channel. The recycle module is connected to the transfer channel to receive the recycling powder, sieves the recycling powder, provides virgin powder, and mixes the virgin powder with the recycling powder. The refilling tank is connected to the recycle module to receive the recycling powder and the virgin powder.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 22, 2020
    Assignee: NATIONAL CHUNG-SHAN INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Yi-Lun Xiao, Li-Tsung Sheng, Shu-San Hsiau, Kuo-Kuang Jen, Chih-Peng Chen, Po-Shen Lin, Chung-Chun Huang
  • Publication number: 20200286878
    Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
    Type: Application
    Filed: May 27, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
  • Patent number: 10771309
    Abstract: A technology is described for updating an Autonomous System Number (ASN) in a Border Gateway Protocol (BGP) routing configuration. An example method may include receiving a request to update a BGP routing configuration on a gateway with an ASN associated with a customer. In response to the request, the BGP routing configuration on the gateway may be updated to replace a default ASN associated with a computing service provider with the ASN associated with the customer. The BGP routing configuration on the gateway may also be updated to allow the ASN associated with the customer to appear in an Autonomous System (AS) path at least twice, thereby allowing for BGP routes to be exchanged between gateways.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 8, 2020
    Inventors: Po-Chun Chen, Mark Edward Stalzer, Andrew Hemstreet Redmon
  • Patent number: 10771766
    Abstract: Various examples with respect to method and apparatus for active stereo vision are described. An apparatus may include an electromagnetic (EM) wave emitter, a first sensor and a second sensor. During operation, the EM wave emitter emits EM waves toward a scene, the first sensor captures a first image of the scene in an infrared (IR) spectrum, and the second sensor captures a second image of the scene in a light spectrum. The first image and second image, when processed, may enable active stereo vision.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 8, 2020
    Assignee: MEDIATEK INC.
    Inventors: Han-Yang Wang, Yu-Chun Chen, Po-Hao Huang, Chao-Chung Cheng, Ying-Jui Chen, Te-Hao Chang
  • Patent number: 10755936
    Abstract: First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jin-Dah Chen, Ming-Feng Shieh, Han-Wei Wu, Yu-Hsien Lin, Po-Chun Liu, Stan Chen
  • Publication number: 20200266228
    Abstract: In some embodiments, the present disclosure relates to an integrated chip having an inter-layer dielectric (ILD) structure along a first surface of a substrate having a photodetector. An etch stop layer is over the ILD structure, and a reflector is surrounded by the etch stop layer and the ILD structure. The reflector has a curved surface facing the substrate at a location directly over the photodetector. The curved surface is coupled between a first sidewall and a second sidewall of the reflector. The reflector has larger thicknesses along the first sidewall and the second sidewall than at a center of the reflector between the first sidewall and the second sidewall.
    Type: Application
    Filed: April 17, 2020
    Publication date: August 20, 2020
    Inventors: Po-Han Huang, Jiech-Fun Lu, Yu-Chun Chen
  • Patent number: 10750002
    Abstract: A communication device includes a first body, a second body, a first audio module, and a second audio module. The second body is rotatably connected to the first body. The first audio module is disposed on the first body. The second audio module is at least partially disposed on the first body. When the second body rotates relatively to the first body to be in a first state to switch the communication device to be in a first operation mode, at least a portion of the first audio module is turned on, and the second audio module is turned off. When the second body rotates relatively to the first body to be in a second state to switch the communication device to be in a second operation mode, the first audio module is turned off, and the second audio module is turned on.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 18, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Ching-Hua Li, Li-Fang Chen, Chen-Hsien Cheng, Yi-Chang Wu, Po-Yueh Lan, Yu-Wei Lai, Kun-Chang Chen, Yi-Chun Lin
  • Publication number: 20200252211
    Abstract: A method for generating a random number is used for a plurality of blocks in a blockchain. The method comprises the steps of: selecting a committee comprising a subset of nodes from the blockchain; executing a distributed key generation to generate a share key and a public key at each of the nodes, wherein the public key further comprises a set of verification keys; broadcasting a share signature from each of the nodes; executing a threshold signature at each of the nodes when a new block is generated; and executing a random number which is a hash value of the threshold signature which is combined from a plurality of partial signature generated from the nodes.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Inventors: TAI-YUAN CHEN, WEI-NING HUANG, PO-CHUN KUO, HAO CHUNG
  • Publication number: 20200252375
    Abstract: A request to establish an encrypted VPN connection between a network external to a provider network connected to the provider network via a dedicated direct physical link and a set of resources of the provider network is received. A new isolated virtual network (IVN) is established to implement an encryption virtual private gateway to be used for the connection. One or more protocol processing engines (PPEs) are instantiated within the IVN, address information of the one or more PPEs is exchanged with the external network and a respective encrypted VPN tunnel is configured between each of the PPEs and the external network. Routing information pertaining to the set of resources is provided to the external network via at least one of the encrypted VPN tunnels, enabling routing of customer data to the set of resources within the provider network from the external network via an encrypted VPN tunnel implemented over a dedicated direct physical link between the external network and the provider network.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 6, 2020
    Applicant: Amazon Technologies, Inc.
    Inventors: Po-Chun Chen, Omer Hashmi, Sanjay Bhal
  • Patent number: 10735292
    Abstract: A physical interconnect having multiple virtual paths is coupled between network devices of independent networks operated by different entities. In one aspect, the interconnect is monitored so that the entities can simultaneously and separately monitor network traffic being exchanged across the interconnect. Each entity can be assigned two virtual paths through the interconnect to pass network traffic through their network device, over the interconnect, through a network device of the other entity, back over the interconnect link and back through their network device. The network devices can be configured to loop back network packets using a variety of loopback configurations. Hardware policers that monitor capacity usage of the virtual paths can also be tested.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 4, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Erik Klayton Klavon, Po-Chun Chen, James Michael Lamanna, Halley Jagarapu, Jagan Selvarajah
  • Publication number: 20200243541
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, in which a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner as the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
    Type: Application
    Filed: April 7, 2020
    Publication date: July 30, 2020
    Inventors: Kun-Hsin Chen, Hsuan-Tung Chu, Tsuo-Wen Lu, Po-Chun Chen