Patents by Inventor Po-Jung Lin
Po-Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250254948Abstract: A high electron mobility transistor and a method for manufacturing the same are disclosed. The high electron mobility transistor includes an epi layer, a source, a drain, a gate structure and a gate metal. The source, the gate structure and the drain locate on the epi layer. The gate structure is located between the source and the drain. The gate structure includes a first doped semiconductor layer with a first width W1, a current suppression layer with a third width W3, and a second doped semiconductor layer with a first width W2, wherein W1>W2, W3=W2. The first doped semiconductor layer is disposed on the epi layer. The current suppression layer is disposed on the first doped semiconductor layer. The second doped semiconductor layer is disposed on the current suppression layer. The gate metal is disposed on the second doped semiconductor layer.Type: ApplicationFiled: December 5, 2024Publication date: August 7, 2025Inventors: WEI-CHIH HO, PO-JUNG LIN
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Patent number: 12336212Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.Type: GrantFiled: November 17, 2022Date of Patent: June 17, 2025Assignee: GLOBALWAFERS CO., LTD.Inventors: Po-Jung Lin, Jia-Zhe Liu
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Publication number: 20250169125Abstract: A high electron mobility transistor includes a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. The buffer layer includes a first buffer region, a second buffer region and a third buffer region. The first buffer region includes a first III-nitride stacked layer disposed on the nucleation layer and a second III-nitride stacked layer disposed on the first III-nitride stacked layer. The second buffer region is doped with carbon and iron. The third buffer region is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the third buffer region. The second III-nitride stacked layer is doped with carbon and iron and has a carbon concentration greater than an iron concentration of the second III-nitride stacked layer.Type: ApplicationFiled: October 22, 2024Publication date: May 22, 2025Applicant: HiPer Semiconductor Inc.Inventors: PO-JUNG LIN, WEI-CHEN YANG
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Patent number: 12283611Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.Type: GrantFiled: May 26, 2022Date of Patent: April 22, 2025Assignee: GlobalWafers Co., Ltd.Inventors: Po Jung Lin, Tzu-Yao Lin
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Publication number: 20240304442Abstract: A method of fabricating an epitaxial structure includes providing a silicon carbide substrate and placing the silicon carbide substrate in a growth chamber; forming a nucleation layer on a surface of the silicon carbide substrate, wherein a process gas required to grow the nucleation layer includes a first gas; a process of growing the nucleation layer includes performing a growth step; the growth step includes performing a first action and then performing a second action; the first action includes introducing the first gas into the growth chamber; the second action includes stopping introducing the first gas into the growth chamber; the growth step is repeated a plurality of times to form the nucleation layer; and forming a nitride epitaxial layer on a surface of the nucleation layer.Type: ApplicationFiled: January 25, 2024Publication date: September 12, 2024Applicant: GLOBALWAFERS CO., LTD.Inventor: PO-JUNG LIN
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Publication number: 20240170564Abstract: An epitaxial structure includes a substrate, a first buffer layer, a second buffer layer, and a channel layer, wherein the first buffer layer is located on a top of the substrate and includes a first portion. The first portion includes a nitride, which is ternary and above, and an aluminum atom concentration of the first portion is less than or equal to 25 at %. The first portion has an element doping, wherein a doping concentration of the element doping of the first portion is greater than or equal to 1×1018 cm?3. The second buffer layer is located on a top of the first buffer layer. The second buffer layer is provided without aluminum and has an element doping. The channel layer is located on a top of the second buffer layer.Type: ApplicationFiled: November 15, 2023Publication date: May 23, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, JIA-ZHE LIU, HONG-CHE LIN, CHIH-YUAN CHUANG
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Publication number: 20240063335Abstract: A light-emitting element structure includes a substrate, a nucleation layer located above the substrate, a buffer layer located above the nucleation layer, a first nitride layer located above the buffer layer and being in contact with the buffer layer, a second nitride layer located above the first nitride layer and being in contact with the first nitride layer, a first semiconductor layer located above the second nitride layer, a light-emitting layer, and a second semiconductor layer located above the light-emitting layer. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer. A dislocation defect density of the second nitride layer is smaller than or equal to 3×109 cm?2. The light-emitting layer is located above the first semiconductor layer and is adapted to emit light when electrons and holes recombine.Type: ApplicationFiled: August 1, 2023Publication date: February 22, 2024Applicant: GLOBALWAFERS CO., LTD.Inventors: JIA-ZHE LIU, PO-JUNG LIN
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Publication number: 20230378278Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and 0?y?1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.Type: ApplicationFiled: July 14, 2023Publication date: November 23, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Jia-Zhe Liu, Chih-Yuan Chuang, Po Jung Lin, Hong Che Lin
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Publication number: 20230360909Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face having an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer having a thickness less than 50 nm on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230360910Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face, and the growth face has an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230357916Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon nitride (SiC) substrate having a carbon face (C-face) without an off-angle; B: form an amorphous structure layer on the C-face of the SiC substrate; C: deposit a first group III nitride layer on the amorphous structure layer; and D: deposit a second group III nitride layer on the first group III nitride layer. By forming the amorphous structure layer, a top surface of the second group III nitride layer could be made to be in a flat and smooth state.Type: ApplicationFiled: February 1, 2023Publication date: November 9, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, HAN-ZONG WU
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Publication number: 20230343588Abstract: A semiconductor structure includes a silicon carbide (SiC) substrate, a nucleation layer and a gallium nitride (GaN) layer. The silicon carbide layer has a first thickness T1. The nucleation layer is located on the silicon carbide layer and has a second thickness T2. The nucleation layer is made of AlGaN (AlGaN), and the second thickness T2 fulfills a thickness range of T1*0.002% to T1*0.006%. The gallium nitride layer is located on the nucleation layer and is separated from the silicon carbide substrate.Type: ApplicationFiled: April 10, 2023Publication date: October 26, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Po Jung Lin, Jia-Zhe Liu
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Publication number: 20230290873Abstract: An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm?3.Type: ApplicationFiled: November 17, 2022Publication date: September 14, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: PO-JUNG LIN, JIA-ZHE LIU
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Publication number: 20230290872Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.Type: ApplicationFiled: November 17, 2022Publication date: September 14, 2023Applicant: GLOBALWAFERS CO., LTD.Inventors: Po-Jung LIN, Jia-Zhe LIU
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Publication number: 20230215925Abstract: A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.Type: ApplicationFiled: October 21, 2022Publication date: July 6, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Po Jung Lin, Ying-Ru Shih, Chenghan Tsao
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Publication number: 20230045328Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.Type: ApplicationFiled: May 26, 2022Publication date: February 9, 2023Applicant: GlobalWafers Co., Ltd.Inventors: Po Jung Lin, Tzu-Yao Lin
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Patent number: 11521480Abstract: An intrusion detection apparatus and method thereof are provided. The intrusion detection apparatus includes a status detection device, a front-end signal processor, a delay device, and a signal sampler. The status detection device is configured to generate an indicating signal according to an opened status of the case. The front-end signal processor receives the indicating signal and performs a noise filtering function on the indicating signal so as to generate a processed indicating signal. The delay device delays the processed indicating signal to generate a delayed indicating signal. The signal sampler samples the processed indicating signal to generate a detection result according to the delayed indicating signal.Type: GrantFiled: August 27, 2021Date of Patent: December 6, 2022Assignee: Wiwynn CorporationInventors: Chi Ming Wu, Yu Shu Kao, Hsieh Ju Tsai, Ye Sheng Lin, Po Jung Lin
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Publication number: 20180230595Abstract: In an embodiment, a vapor phase film-forming apparatus 10 includes a susceptor 12 for holding a film forming substrate 14. A flow channel 40 is formed horizontally by the opposite surface 20 facing the susceptor 12. In the flow channel 40, a material gas introduction port 42 and material gas and a purge gas exhaust port 48 are provided. On the opposite surface 20, many purge gas nozzles 36 are provided and divided into a plurality of purge areas PE1-PE 3. Mass flow controllers (MFCs) 52A-52C and 62A-62C for adjusting the flow rate for each purge area are provided in each purge area. Then, the mass flow rate of the purge gas is controlled by the MFCs 52A-52C and 62A-62C for each purge area.Type: ApplicationFiled: February 9, 2018Publication date: August 16, 2018Inventors: Noboru Suda, Takahiro Oishi, Junji Komeno, Po-Jung Lin
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Publication number: 20180163304Abstract: A gas injector includes a base plate, a channel cover plate disposed above the base plate, and a plurality of separating plates disposed between the base plate and the channel cover plate. The separating plates are separated from each other to define a plurality of channels with space for transferring reactant gas from a center of the base plate towards a periphery of the base plate, thereby defining gas outlets associated with the channels from which reactant gas is ejected towards a wafer.Type: ApplicationFiled: February 12, 2018Publication date: June 14, 2018Inventors: Po-Jung Lin, Tsan-Hua Huang, Junji Komeno, Noboru Suda
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Publication number: 20180094353Abstract: A gas injector includes a base plate, a center sleeve cover, an intake body, an inner cover and an outer cover. The base plate includes a plurality of channels. The center sleeve cover is operatively coupled with the base plate to form a first cavity, a wall of the center sleeve cover having a plurality of first communicating openings correspondingly connected to first channels. The intake body includes a top portion, an inner wall and an outer wall. The inner cover is disposed between the center sleeve cover and the inner wall to result in a second cavity, the inner cover having a plurality of second communicating openings correspondingly connected to second channels. The outer cover is disposed between the inner wall and the outer wall to result in a third cavity, the outer cover having a plurality of third communicating openings correspondingly connected to third channels.Type: ApplicationFiled: September 21, 2017Publication date: April 5, 2018Inventors: Tsan-Hua Huang, Po-Jung Lin