Abstract: A method includes attaching a package component to a package substrate, the package component includes: an interposer disposed over the package substrate; a first die disposed along the interposer; and a second die disposed along the interposer, the second die being laterally adjacent the first die; attaching a first thermal interface material to the first die, the first thermal interface material being composed of a first material; attaching a second thermal interface material to the second die, the second thermal interface material being composed of a second material different from the first material; and attaching a lid assembly to the package substrate, the lid assembly being further attached to the first thermal interface material and the second thermal interface material.

Abstract: A method includes etching a gate stack in a wafer to form a trench, depositing a silicon nitride liner extending into the trench, and depositing a silicon oxide layer. The process of depositing the silicon oxide layer includes performing a treatment process on the wafer using a process gas including nitrogen and hydrogen, and performing a soaking process on the wafer using a silicon precursor.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.

Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

Abstract: A method for performing network control in a wireless communications system and associated apparatus are provided. The method may include: carrying a set of link information in a preamble of a first data transmission frame transmitted from the first network device to a second network device, wherein the set of link information may include at least one indication among the following indications: a destination device indication, a device assignment indication and a transmission power control indication; wherein a third network device is arranged to monitor wireless transmission in the wireless communications system to obtain the set of link information from the first data transmission frame, and determine spatial reuse (SR) transmission availability of the third network device based on the set of link information.

Abstract: A light-emitting element structure includes a substrate, a nucleation layer located above the substrate, a buffer layer located above the nucleation layer, a first nitride layer located above the buffer layer and being in contact with the buffer layer, a second nitride layer located above the first nitride layer and being in contact with the first nitride layer, a first semiconductor layer located above the second nitride layer, a light-emitting layer, and a second semiconductor layer located above the light-emitting layer. A film thickness of the first nitride layer is smaller than a film thickness of the second nitride layer. A dislocation defect density of the second nitride layer is smaller than or equal to 3×109 cm?2. The light-emitting layer is located above the first semiconductor layer and is adapted to emit light when electrons and holes recombine.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and 0?y?1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.

Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon nitride (SiC) substrate having a carbon face (C-face) without an off-angle; B: form an amorphous structure layer on the C-face of the SiC substrate; C: deposit a first group III nitride layer on the amorphous structure layer; and D: deposit a second group III nitride layer on the first group III nitride layer. By forming the amorphous structure layer, a top surface of the second group III nitride layer could be made to be in a flat and smooth state.

Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face, and the growth face has an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.

Abstract: A method of manufacturing an epitaxial structure includes steps of: A: provide a silicon carbide (SiC) substrate, wherein a silicon face (Si-face) of the SiC substrate is taken as a growth face having an off-angle relative to the Si-face of the SiC substrate; B: deposit a nitride angle adjustment layer having a thickness less than 50 nm on the growth face of the SiC substrate through physical vapor deposition (PVD); C: deposit a first group III nitride layer on the nitride angle adjustment layer; and D: deposit a second group III nitride layer on the first group III nitride layer. Through the method of manufacturing the epitaxial structure, when the silicon face of the silicon carbide substrate has the off-angle, the problem of a poor epitaxial quality of the first group III nitride layer and a poor epitaxial quality of the second group III nitride layer could be effectively relieved.

Abstract: A semiconductor structure includes a silicon carbide (SiC) substrate, a nucleation layer and a gallium nitride (GaN) layer. The silicon carbide layer has a first thickness T1. The nucleation layer is located on the silicon carbide layer and has a second thickness T2. The nucleation layer is made of AlGaN (AlGaN), and the second thickness T2 fulfills a thickness range of T1*0.002% to T1*0.006%. The gallium nitride layer is located on the nucleation layer and is separated from the silicon carbide substrate.

Abstract: An improved high electron mobility transistor (HEMT) structure includes in order a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer, wherein the buffer layer includes a dopant. The channel layer having a dopant doping concentration less than that of the buffer layer. A two-dimension electron gas is formed in the channel layer along an interface between the channel layer and the barrier layer. A dopant doping concentration of the channel layer at an interface between the channel layer and the barrier layer is equal to or greater than 1×1015 cm?3.

Abstract: An improved high electron mobility transistor (HEMT) structure includes a substrate, a nitride nucleation layer, a nitride buffer layer, a nitride channel layer, and a barrier layer. The nitride buffer layer includes a metal dopant. The nitride channel layer has a metal doping concentration less than that of the nitride buffer layer. A two-dimensional electron gas is formed in the nitride channel layer along an interface between the nitride channel layer and the barrier layer. A metal doping concentration X at an interface between the nitride buffer layer and the nitride channel layer is defined as the number of metal atoms per cubic centimeter, and a thickness Y of the nitride channel later is in microns (?m) and satisfies Y?(0.2171)ln(X)?8.34, thereby reducing an influence of the metal dopant to a sheet resistance value of the nitride channel layer and providing the improved HEMT structure having a better performance.

Abstract: A semiconductor structure, including a substrate, a first nitride layer, a polarity inversion layer, a second nitride layer, and a third nitride layer, is provided. The first nitride layer is located on the substrate. The polarity inversion layer is located on a surface of the first nitride layer to convert a non-metallic polarity surface of the first nitride layer into a metallic polarity surface of the polarity inversion layer. The second nitride layer is located on the polarity inversion layer. The third nitride layer is located on the second nitride layer. The substrate, the first nitride layer, the polarity inversion layer, and the second nitride layer include iron element.

Abstract: A semiconductor structure includes a substrate, a first nitride layer, a second nitride layer, a third nitride layer, and a polarity inversion layer. The first nitride layer is formed on the substrate, and the polarity inversion layer formed at a surface of the first nitride layer converts a non-metallic polar surface of the first nitride layer into a metallic polar surface of the polarity inversion layer. The second nitride layer is formed on the polarity inversion layer. The third nitride layer is formed on the second nitride layer.

Abstract: An intrusion detection apparatus and method thereof are provided. The intrusion detection apparatus includes a status detection device, a front-end signal processor, a delay device, and a signal sampler. The status detection device is configured to generate an indicating signal according to an opened status of the case. The front-end signal processor receives the indicating signal and performs a noise filtering function on the indicating signal so as to generate a processed indicating signal. The delay device delays the processed indicating signal to generate a delayed indicating signal. The signal sampler samples the processed indicating signal to generate a detection result according to the delayed indicating signal.

Abstract: In an embodiment, a vapor phase film-forming apparatus 10 includes a susceptor 12 for holding a film forming substrate 14. A flow channel 40 is formed horizontally by the opposite surface 20 facing the susceptor 12. In the flow channel 40, a material gas introduction port 42 and material gas and a purge gas exhaust port 48 are provided. On the opposite surface 20, many purge gas nozzles 36 are provided and divided into a plurality of purge areas PE1-PE 3. Mass flow controllers (MFCs) 52A-52C and 62A-62C for adjusting the flow rate for each purge area are provided in each purge area. Then, the mass flow rate of the purge gas is controlled by the MFCs 52A-52C and 62A-62C for each purge area.

Abstract: A gas injector includes a base plate, a channel cover plate disposed above the base plate, and a plurality of separating plates disposed between the base plate and the channel cover plate. The separating plates are separated from each other to define a plurality of channels with space for transferring reactant gas from a center of the base plate towards a periphery of the base plate, thereby defining gas outlets associated with the channels from which reactant gas is ejected towards a wafer.

Abstract: A gas injector includes a base plate, a center sleeve cover, an intake body, an inner cover and an outer cover. The base plate includes a plurality of channels. The center sleeve cover is operatively coupled with the base plate to form a first cavity, a wall of the center sleeve cover having a plurality of first communicating openings correspondingly connected to first channels. The intake body includes a top portion, an inner wall and an outer wall. The inner cover is disposed between the center sleeve cover and the inner wall to result in a second cavity, the inner cover having a plurality of second communicating openings correspondingly connected to second channels. The outer cover is disposed between the inner wall and the outer wall to result in a third cavity, the outer cover having a plurality of third communicating openings correspondingly connected to third channels.

Abstract: The present invention relates to a gas distributing injector applied in MOCVD reactor. The gas distributing injector comprises at least one gas distributing layer for distributing different gases. The distributing layer is a single-layered structure. The distributing layer comprises a disk-shaped body, a plurality of first gas channels, a plurality of second gas channels, and a plurality of third gas channels. The first gas channels, the second gas channels, and the third gas channels are radially distributed on the same plane in the disk-shaped body. Different gases are distributed or fed into different gas channels (such as the first gas channels, the second gas channels, and the third gas channels) and transported by different gas channels. Through different gas channels, different gases are transversely injected into the MOCVD reactor on the same plane respectively. Therefore, the gas distributing injector of this invention can distribute different gases by a single-layered structure.