Abstract: An image processing system includes a first memory for storing a first image data, the first image data having a plurality of pixels; a second memory for storing at least one mapping table, the mapping table recording the mapped positions of at least a portion of pixels; a direct memory access control unit for accessing the first memory and the second memory; a first processing unit for accessing the first image data and the mapping table via the direct memory access control unit so as to produce a second image data; and a third memory for storing the second image data.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: An processing method is used for processing an image file of an image, in which the image is divided into a plurality of image blocks, and at least one row of the minimum coded units sequentially define the image as a plurality of bands. The processing method includes the following steps. An image file of an image is supplied, in which the image file includes a bit stream and exchangeable image file (EXIF) data. A band indicator of the EXIF data is read according to an expanded range. A segment in the bit stream corresponding to a band encompassed by the expanded range is decoded according to the read band indicator corresponding to the band of the expanded range, so as to obtain the band.

Abstract: An image pipeline device is used for processing an image. The device comprises an external memory, a direct memory access (DMA), an image pipeline controller, and a filter layer. The image pipeline controller comprises a physical memory allocation (PMA) having a physical buffer unit, and a first array controller for configuring the physical buffer unit as a corresponding first logic buffer unit. The filter layer comprises a first filter set electrically connected to the first array controller correspondingly and having a plurality of filters. The first filter set receives the image through the first array controller, processes the image selectively according to the first logic buffer unit and the filters, and stores the processed image back to the external memory through the DMA.

Abstract: A video processing apparatus and a video processing method are used to capture a view region as a video result. The video processing apparatus includes a video sensor, a temporary memory, and a video pipeline. The video sensor captures the view region at a sensor frame rate and generates a video having a plurality of frames. The video pipeline receives one of the frames directly from the video sensor to serve as a first frame. The video pipeline processes the first frame to generate a temporary result frame, and then generates a video result at a video frame rate according to the temporary result frame and a second frame directly received from the video sensor, wherein the video frame rate is smaller than the sensor frame rate. The video processing method captures the view region as the video result by using the video processing apparatus.

Abstract: An update method for look up table (LUT) is suitable for an image processing apparatus. The image processing apparatus includes a multiple-interpolation lookup table device having an execution LUT, and the LUT update method updates the multiple-interpolation lookup table device according to a source LUT. The update method includes the steps of dividing the source LUT into a plurality of sub LUTs; and using the sub LUTs to respectively update content of the execution LUT in a plurality of vertical blanking intervals (VBIs).

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: A base station (BS), a subordinated station (SS) and the transmission methods thereof for use in a multi-input multi-output (MIMO) network are provided. The BS stores resource allocation information about the MIMO network and an SS list, and generate a super frame according to the resource allocation information and the SS list. The super frame comprises a pilot pattern which comprises a plurality of pilots and data. The BS and SS both considers the pilot pattern as an identifier of the SS. When there are communications occurred between the BS and the SS, the BS/SS will confirm whether the pilot pattern of the super frame matches the identifier of the SS to reduce interference from other stations in the MIMO network.

Abstract: An image processing system includes a first memory for storing a first image data, the first image data having a plurality of pixels; a second memory for storing at least one mapping table, the mapping table recording the mapped positions of at least a portion of pixels; a direct memory access control unit for accessing the first memory and the second memory; a first processing unit for accessing the first image data and the mapping table via the direct memory access control unit so as to produce a second image data; and a third memory for storing the second image data.

Abstract: A boot system which uses a NAND flash is disclosed. The boot system is used for a digital camera, and it comprises a NAND flash, a flash control module, a processing module, and an IO bridge. The processing module includes a cache memory. When booting the digital camera, the cache memory reads a boot code from the NAND flash to the processing module for processing a booting operation.