Abstract: An optical device includes a carrier including a light transmitting layer and a light shielding layer disposed on the light transmitting layer. The optical device further includes a light emitter disposed on the carrier and a light detector disposed on the carrier. The optical device further includes a light transmitting encapsulant encapsulating the light emitter and the light detector, and a light shielding wall disposed in the light transmitting encapsulant and in contact with the light transmitting encapsulant and the light shielding layer.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A semiconductor device includes a dummy fin structure disposed over a substrate, a dummy gate structure disposed over a part of the dummy fin structure, a first interlayer dielectric layer in which the dummy gate structure is embedded, a second interlayer dielectric layer disposed over the first interlayer dielectric layer, and a resistor wire formed of a conductive material and embedded in the second interlayer dielectric layer. The resistor wire overlaps the dummy gate structure in plan view.

Abstract: A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.

Abstract: The invention creates a support for cell culture and cell sheet detachment which has a substrate, whose surface is coated with a conjugate having a disulfide bond-containing amino acid as a spacer and a biopolymer enhancing cell attachment, migration or differentation. Unexpectedly, after being seeded on the support, the cells grow to form one or more layers of cell sheets and the cell sheets can be easily detached from the support by adding a reductant to cleave the disulfide bond. Accordingly, the invention provides a simple and non-toxic method for detachment of cell sheets.

Abstract: An exemplary integrated circuit comprises: a first device gate disposed over the first device region, the first device gate comprising a first interfacial layer and a first dielectric layer; a second device gate disposed over the second device region, the second device gate comprising a second interfacial layer and a second dielectric layer; and a third device gate disposed over the third device region, the third device gate comprising a third interfacial layer and a third dielectric layer, wherein the first interfacial layer, the second interfacial layer, and the third interfacial layer are different from each other in at least one of a thickness and an interfacial material.

Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Abstract: A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

Abstract: A method including providing a substrate having a first region, a second region, and a third region defined thereupon. A first interfacial layer is formed over the first region, the second region, and the third region. The first interfacial layer is etched to remove a portion of the first interfacial layer from the first region and a portion of the first interfacial layer from the second region. Etching of the first interfacial layer defines a gate stack within the third region. After the etching of the first interfacial layer, a second interfacial layer is formed over at least a portion of the second region. The second interfacial layer is etched to define a gate stack within the second region. After the etching of the second interfacial layer, a third interfacial layer is formed on the substrate over at least a portion of the first region to define a gate stack within the first region.

Abstract: A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion of the first dielectric layer to expose a second region of the substrate; forming a second dielectric layer having a second thickness over the second region of the substrate; removing a second portion of the first dielectric layer to expose a third region of the substrate; forming a third dielectric layer having a third thickness over the third region of the substrate; and forming a first plurality of gate stacks comprising the first dielectric layer in a first region of the substrate, a second plurality of gate stacks comprising the second dielectric layer in the second region of the substrate, and a third plurality of gate stacks comprising the third dielectric layer in the third region of the substrate.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate having regions for an n-type field-effect transistor (nFET) core, an input/output nFET (nFET IO), a p-type field-effect transistor (pFET) core, an input/output pFET (pFET IO), and a high-resistor, forming an oxide layer on the IO regions of the substrate, forming an interfacial layer on the substrate and the oxide layer, depositing a high-k (HK) dielectric layer on the interfacial layer, depositing a first capping layer of a first material on the HK dielectric layer, depositing a second capping layer of a second material on the HK dielectric layer and on the first capping layer, depositing a work function (WF) metal layer on the second capping layer, depositing a polysilicon layer on the WF metal layer, and forming gate stacks on the regions of the substrate.