Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a fin structure over a substrate in a first direction, forming a first gate stack, a second gate stack and a third gate stack across the fin structure, removing the first gate stack to form a trench, depositing a cutting structure in the trench, and forming a first contact plug between the cutting structure and the second gate stack and a second contact plug between the second gate stack and the third gate stack. The fin structure is cut into two segments by the trench. A first dimension of the first contact plug in the first direction is greater than a second dimension of the second contact plug in the first direction.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first trench in the base and between the first fin and the second fin. The method includes forming an isolation layer over the base and in the first trench. The first fin and the second fin are partially in the isolation layer. The method includes forming a first gate stack over the first fin and the isolation layer. The method includes forming a second gate stack over the second fin and the isolation layer. The method includes removing a bottom portion of the base. The isolation layer passes through the base after the bottom portion of the base is removed.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: An electronic device includes a display surface, a back surface with a first portion and a second portion, and a support assembly. The support assembly includes a first, second, and third boards. The first board includes a first surface, detachably covering the first portion, and a second surface. The second board is bendably connected to the first board and combined with the second portion. The third board includes a pivoted end and a free end. The pivoted end is pivotally connected to the second surface and covers the second board and a portion of the first board. When the first board rotates relative to the first portion, the third board also rotates relative to the second board, the second surface faces the third board, and the second board simultaneously moves along the third board. Accordingly, the display surface is raised up a distance relative to the free end.

Abstract: A foldable electronic device is disclosed and includes a first body, a second body, a hinge mechanism, and a cover. The hinge mechanism includes a first rack plate disposed to the first body, a second rack plate disposed to the second body, a first gear shaft meshed with the first rack plate, and a second gear shaft meshed with the second rack plate and the first gear shaft. The cover is movably disposed on the hinge mechanism and covers the hinge mechanism. When the second body rotates relative to the first body, the second rack plate, the second gear shaft, the first gear shaft and the first rack plate rotate in sequence, the first rack plate and the second rack plate abut against the cover, so the cover is away from the hinge mechanism and separated from the first body and the second body.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A control method is provided, applied to an electronic device. The electronic device includes a screen and a knob module. The control method includes: receiving a trigger signal to enable the knob module, and displaying an operating interface corresponding to the knob module on the screen according to the trigger signal, where the operating interface includes a plurality of functional regions that is arranged annularly, and the functional regions are configured to display a plurality of function options, where one of the functional regions shows a marked state; switching the functional region corresponding to the marked state according to a first input signal from the knob module; and selecting the functional region corresponding to the marked state according to a second input signal from the knob module.

Abstract: An electronic device includes a first body, a first pivot structure, a second body, a first plate, a second plate, a third plate, a second pivot structure, and a third pivot structure. The first body includes a first region and a second region. The second body includes a third region and a fourth region. The second body is pivotally connected to the first body by the first pivot structure. The first plate is disposed corresponding to the first region. The second plate is disposed corresponding to the third region. The third plate is disposed corresponding to the fourth region. One side of the third plate is adjacent to the second plate, and the other side of the third plate is detachably coupled to the first plate. The second pivot structure connects the first body and the first plate. The third pivot structure connects the second body and the second plate.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A foldable electronic device is disclosed and includes a first body, a second body, a hinge mechanism, and a cover. The hinge mechanism includes a first rack plate disposed to the first body, a second rack plate disposed to the second body, a first gear shaft meshed with the first rack plate, and a second gear shaft meshed with the second rack plate and the first gear shaft. The cover is movably disposed on the hinge mechanism and covers the hinge mechanism. When the second body rotates relative to the first body, the second rack plate, the second gear shaft, the first gear shaft and the first rack plate rotate in sequence, the first rack plate and the second rack plate abut against the cover, so the cover is away from the hinge mechanism and separated from the first body and the second body.

Abstract: An electronic device includes a display surface, a back surface with a first portion and a second portion, and a support assembly. The support assembly includes a first, second, and third boards. The first board includes a first surface, detachably covering the first portion, and a second surface. The second board is bendably connected to the first board and combined with the second portion. The third board includes a pivoted end and a free end. The pivoted end is pivotally connected to the second surface and covers the second board and a portion of the first board. When the first board rotates relative to the first portion, the third board also rotates relative to the second board, the second surface faces the third board, and the second board simultaneously moves along the third board. Accordingly, the display surface is raised up a distance relative to the free end.

Abstract: A control method is provided, applied to an electronic device. The electronic device includes a screen and a knob module. The control method includes: receiving a trigger signal to enable the knob module, and displaying an operating interface corresponding to the knob module on the screen according to the trigger signal, where the operating interface includes a plurality of functional regions that is arranged annularly, and the functional regions are configured to display a plurality of function options, where one of the functional regions shows a marked state; switching the functional region corresponding to the marked state according to a first input signal from the knob module; and selecting the functional region corresponding to the marked state according to a second input signal from the knob module.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first transistor in the first region, a second transistor in the first region, and a third transistor in the second region. The first transistor includes a first channel layer and a first gate dielectric layer on the first channel layer. The second transistor includes a second channel layer and a second gate dielectric layer on the second channel layer. The second gate dielectric layer is thicker than the first gate dielectric layer. The third transistor includes a third channel layer and a third gate dielectric layer on the third channel layer. The third gate dielectric layer is thicker than the second gate dielectric layer.

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a first, a second, a third, and a fourth fin structures over a substrate. The method also includes forming a first spacer layer over sidewalls of the first and the second fin structures. The method further includes forming a second spacer layer over the first spacer layer and sidewalls of the third and the fourth fin structures. In addition, the method includes forming a first blocking fin between the first and the second fin structures. The first blocking fin is separated from the first fin structure by portions of the first spacer layer and the second spacer layer. The method includes forming a second blocking fin between the third and the fourth fin structures. The second blocking fin is separated from the third fin structure by a portion of the second spacer layer.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.