Patents by Inventor Po-Shen Lai
Po-Shen Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136246Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Patent number: 11967547Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.Type: GrantFiled: August 26, 2021Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11967582Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.Type: GrantFiled: April 24, 2023Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11955455Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.Type: GrantFiled: July 25, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh
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Publication number: 20240088095Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
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Patent number: 11915991Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.Type: GrantFiled: June 29, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
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Patent number: 11087803Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.Type: GrantFiled: June 18, 2020Date of Patent: August 10, 2021Assignee: SanDisk Technologies LLCInventors: Yuheng Zhang, Po-Shen Lai, Hao Su
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Publication number: 20200321037Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.Type: ApplicationFiled: June 18, 2020Publication date: October 8, 2020Applicant: SanDisk Technologies LLCInventors: Yuheng Zhang, Po-Shen Lai, Hao Su
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Patent number: 10777240Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.Type: GrantFiled: June 26, 2019Date of Patent: September 15, 2020Assignee: SanDisk Technologies LLCInventors: Yuheng Zhang, Po-Shen Lai, Hao Su
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Publication number: 20200286533Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core-Timing-Control (CTC) signals. The CTC signals are used to control voltages that are applied in the memory structure. For example, CTC signals may be used to control the timing of voltages applied to word lines, bit lines, select lines, and other elements or control lines in the memory core. The microcontroller is configured to output CTC signals having many different variations under various modes/parameter conditions. The apparatus may include storage containing reaction data according to dynamic conditions. The microcontroller may be configured to lookup or compute the CTC signals based on the dynamic conditions and the reaction data. Various data storage formats are disclosed, which can be used to efficiently store many varieties of data with minimum usage of memory.Type: ApplicationFiled: June 26, 2019Publication date: September 10, 2020Applicant: SanDisk Technologies LLCInventors: Yuheng Zhang, Po-Shen Lai, Hao Su
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Patent number: 10635526Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.Type: GrantFiled: March 23, 2018Date of Patent: April 28, 2020Assignee: SanDisk Technologies LLCInventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
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Publication number: 20180357123Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.Type: ApplicationFiled: March 23, 2018Publication date: December 13, 2018Applicant: SanDisk Technologies LLCInventors: Yibo Yin, Henry Zhang, Po-Shen Lai, Vijay Chinchole, Spyridon Georgakis, Yan Li, Hiroyuki Mizukoshi, Toru Miwa, Jayesh Pakhale, Tz-Yi Liu
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Patent number: 8558566Abstract: A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.Type: GrantFiled: April 18, 2011Date of Patent: October 15, 2013Assignee: SanDisk Technologies Inc.Inventors: Po-Shen Lai, Paul A. Lassa, Paul C. Paternoster
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Patent number: 8347251Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.Type: GrantFiled: December 31, 2007Date of Patent: January 1, 2013Assignee: SanDisk CorporationInventors: Paul Paternoster, Vaibhavi Sabharanjak, Po-Shen Lai
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Patent number: 8135944Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.Type: GrantFiled: March 14, 2007Date of Patent: March 13, 2012Assignee: SanDisk Technologies Inc.Inventors: Paul Lassa, Paul Paternoster, Po-Shen Lai, Yongliang Wang
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Patent number: 8102062Abstract: Methods and systems for forming a variety of integrated circuits, having quite different interfaces and packages, from a single manufactured die. Preferably the die has bond pads for at least a first mode of operation positioned along only two of its four sides, and these bond pads are sufficient to construct a multi-chip module in which the die is functional in the first mode of operation. Many of the pads on these two sides are duplicated on third and/or fourth sides, except that power management circuitry prevents wasteful capacitive current onto whichever of the duplicated pads is not connected out. Optionally the third and/or fourth sides can be used for connections needed for a mode which is not available with two sides only.Type: GrantFiled: December 28, 2007Date of Patent: January 24, 2012Assignee: SanDisk Technologies Inc.Inventors: Paul A. Lassa, Paul C. Paternoster, Po-Shen Lai
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Publication number: 20110283055Abstract: A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.Type: ApplicationFiled: April 18, 2011Publication date: November 17, 2011Inventors: Po-Shen Lai, Paul A. Lassa, Paul C. Paternoster
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Patent number: 7928746Abstract: A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.Type: GrantFiled: December 28, 2007Date of Patent: April 19, 2011Assignee: SanDisk CorporationInventors: Po-Shen Lai, Paul A. Lassa, Paul C. Paternoster
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Patent number: 7875996Abstract: An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.Type: GrantFiled: December 21, 2007Date of Patent: January 25, 2011Assignee: SanDisk CorporationInventors: Daniel P. Nguyen, Steve X. Chi, Po-Shen Lai
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Patent number: 7859134Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.Type: GrantFiled: December 21, 2007Date of Patent: December 28, 2010Assignee: SanDisk CorporationInventors: Steve X. Chi, Yongliang Wang, Ekram Hossain Bhuiyan, Daniel P. Nguyen, Vincent Anthony Condito, Po-Shen Lai