Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

Abstract: An integrated circuit (IC) having a selectively-designated electromagnetic compatibility (EMC) performance characteristic. The IC includes an IC die having an input or output (I/O) node. A first I/O cell of a first type associated with the I/O node provides a first EMC performance characteristic, and a second I/O cell of a second type associated with the I/O node provides a second EMC performance characteristic different from the first EMC performance characteristic. A first bonding pad is electrically coupled with the first I/O cell, and a second bonding pad is electrically coupled with the second I/O cell. The IC die can be packaged into a packaged IC having an I/O pin corresponding to the I/O node. The I/O pin is wired to one of either the first bonding pad or the second bonding pad, but not to the other, such that a pinout for the I/O node is preferentially provided having one of either the first EMC performance characteristic or the second EMC performance characteristic.

Abstract: An integrated circuit (IC) includes an output driver circuit portion that is electrically configurable, via a configuration input, to operate in either a first mode or a second mode corresponding to an indication of a condition of the IC, such as a supply voltage indication, the first mode and the second mode having different drive characteristics. A configuration interface circuit portion as part of the improved IC is adapted to selectively override the configuration input to configure operation of the output driver circuit portion in either the first mode or the second mode based on a drive strength control input, regardless of the condition of the IC.

Abstract: A method for operating an electronic product having an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product selects a low-power sub-module or high-power sub-module of the capless regulator module for use in a power-up phase of the ASIC. Control logic of the ASIC determines if an external capacitance is present. If so, then the high-power capless sub-module is used during a power-up phase of the ASIC; if not only the low-power capless sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: A method for operating an electronic product having an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product utilizes control logic of the ASIC device responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Abstract: An electronic product includes an application specific semiconductor circuit (ASIC) including in its circuitry both a linear regulator module for use with an optional external capacitance and a capless regulator module coupled to internal capacitance of the product. The capless regulator module includes both a low-power sub-module and a high-power sub-module. Control logic of the ASIC is configured to determine if an external capacitance is present. If so, the control logic causes the high-power capless regulator sub-module to be used during a power-up phase of the ASIC; if not, only the low-power capless regulator sub-module is used during the power-up phase of the ASIC. After power-up of the ASIC, the control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation or it may select one or the other for all times of post-power-up operation.

Abstract: An electronic product includes an application specific semiconductor chip (ASIC) device which includes in its circuitry both a linear regulator module configured to be coupled to an optional external capacitance and a capless regulator module configured to be coupled to internal capacitance of the electronic product. Control logic of the ASIC device is responsive to a regulator selection signal for selecting one of the linear regulator module and the capless regulator module for use in powering the ASIC device. The control logic may select the linear regulator module for certain times of operation and the capless regulator module for other times of operation.

Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits. Alternatively, the separately powered circuits need not be data interface circuits.

Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits.

Abstract: A plurality of separately powered data interface circuits, a controller circuit, and power switch circuits that collectively enable a supply of power to only one of the data interface circuits and disable the supply of power to the other data interface circuits.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a memory controller that determines whether a complete frame is stored in the random access memory and also determines an amount of data available to be read from the oldest received frame. A host CPU is able to access this information and determine whether to read the data or read the data at a later time.

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data between a host computer bus and a packet switched network. The network interface device includes a read controller and read offset register that stores read pointer information. The host CPU programs the read offset register to any particular value so that the read controller will read data from a desired starting point. In this manner, the host CPU is able to skip parts of a frame stored in the random access memory.

Abstract: A universal interface for communicating information to a proprietary physical interface. At least one output module is provided for transmitting information and an input module is provided for receiving the information. The output module and the input module are configured according to communication parameters of a predetermined type of physical interface to which the output module and the input module interface such that communication of the information is facilitated therebetween.

Abstract: A communication interface for processing errors between network devices. The communication interface includes an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom, and an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by, checking parity of the parity information of the output information received from the first network device, terminating the output information when an error in the parity is detected, and recovering a boundary of the output information when an error in the output control information is detected.

Abstract: A protocol and header format of a network architecture for communication between a plurality of network devices. In particular, the data frame is resolved at the source device to ascertain the data frame type, and the data frame is forwarded with a virtual network identifier and priority information from the source device to a destination device of the network. The forwarded data frame also includes control information.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. Read and write counters are each implemented as gray code counters that increment a corresponding pointer value by changing a single bit. A synchronization circuit selectively sets a full or empty flag based on an asynchronous comparison of the read and write pointer values. Use of gray code counters for the read pointer value and write pointer value ensures accurate comparisons in a multi-clock environment.

Abstract: A network interface includes a multiplexer that selectively supplies either a stored address from an address holding register, or a reload address from a reload address holding register, to a random access buffer memory based on a done delay signal (DMA_DONE_DLY). The done delay signal is generated by an advance signal generator in response to detection of a target initiated termination request on the PCI bus during a DMA data transfer from the random access buffer memory to the target. if the PCI bus transfer is interrupted, the reload address is supplied to the random access buffer memory to enable data output holding registers to be reloaded with the data lost by the target during the interrupted DMA transfer. The array of data output holding registers are capable of recovering from the interrupted PCI bus transfer and output the data set which the target (e.g., the host system memory) expects to receive.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.