Patents by Inventor Po-Shen Lin

Po-Shen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136246
    Abstract: A semiconductor device includes a package structure, a first heat spreader, and a second heat spreader. The first heat spreader is aside the package structure. The second heat spreader is in physical contact with the first heat spreader. The second heat spreader covers a top surface and sidewalls of the package structure. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11967547
    Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240120294
    Abstract: A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 11, 2024
    Inventors: Shu-Shen YEH, Chin-Hua WANG, Kuang-Chun LEE, Po-Yao LIN, Shyue-Ter LEU, Shin-Puu JENG
  • Patent number: 11955455
    Abstract: A method includes bonding a first package component over a second package component. The second package component includes a plurality of dielectric layers, and a plurality of redistribution lines in the plurality of dielectric layers. The method further includes dispensing a stress absorber on the second package component, curing the stress absorber, and forming an encapsulant on the second package component and the stress absorber.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Chien-Sheng Chen, Po-Yao Lin, Po-Chen Lai, Shu-Shen Yeh
  • Publication number: 20240096731
    Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Publication number: 20240096778
    Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 21, 2024
    Inventors: Ya-Huei LEE, Shu-Shen YEH, Kuo-Ching HSU, Shyue-Ter LEU, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240096822
    Abstract: A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Inventors: Chia-Kuei HSU, Ming-Chih YEW, Shu-Shen YEH, Che-Chia YANG, Po-Yao LIN, Shin-Puu JENG
  • Publication number: 20240087974
    Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240088063
    Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.
    Type: Application
    Filed: November 23, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240088061
    Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
  • Publication number: 20240088095
    Abstract: A method for forming a chip package structure. The method includes bonding first connectors over a front surface of a semiconductor wafer. The method also includes dicing the semiconductor wafer from a rear surface of the semiconductor wafer to form semiconductor dies and mounting first and second semiconductor dies in the semiconductor dies over a top surface of the interposer substrate. The method further forming an encapsulating layer over the top surface of the interposer substrate to cover the first semiconductor die and the second semiconductor die. A first sidewall of the first semiconductor die faces a second sidewall of the second semiconductor die, and upper portions of the first sidewall and the second sidewall have a tapered contour, to define a top die-to-die distance and a bottom die-to-die distance that is less than the top die-to-die distance.
    Type: Application
    Filed: November 24, 2023
    Publication date: March 14, 2024
    Inventors: Chin-Hua WANG, Shin-Puu JENG, Po-Yao LIN, Po-Chen LAI, Shu-Shen YEH, Ming-Chih YEW, Yu-Sheng LIN
  • Patent number: 11915991
    Abstract: A semiconductor device includes a substrate, a package structure, a first heat spreader, and a second heat spreader. The package structure is disposed on the substrate. The first heat spreader is disposed on the substrate. The first heat spreader surrounds the package structure. The second heat spreader is disposed on the package structure. The second heat spreader is connected to the first heat spreader. A material of the first heat spreader is different from a material of the second heat spreader.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Yu-Sheng Lin, Po-Chen Lai, Shin-Puu Jeng
  • Patent number: 11633824
    Abstract: The present invention discloses a grinding cavity body of multiple vibration sources, in which a plurality of ultrasonic vibration sources are disposed, capable of controlling the multi-directional macroscopic medium flow, making benefits to the vibration medium (the abrasive of the slurry) to enter the fine structure of the workpiece to be processed, and to the abrasive to vibrate itself slightly to enhance the performance of abrasive to the workpiece which needs to be ground.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 25, 2023
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Po-Shen Lin, Ming-Wei Liu, Chih-Peng Chen, Kuo-Kuang Jen
  • Patent number: 11628539
    Abstract: The present invention discloses a multi-dimensional vibration grinding cavity body. By adjusting amplitudes (power) and frequencies of the multi-dimensional ultrasonic vibration source, such that the multi-directional macroscopic flow is formed in the cavity body while keeping the vibration medium to have the original characteristics to improve the performance of grinding of slurry.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 18, 2023
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Po-Shen Lin, Ming-Wei Liu, Chih-Peng Chen, Kuo-Kuang Jen
  • Patent number: 11065814
    Abstract: The present application provides not only a heating device for additive manufacturing but also a heating module and a manufacturing apparatus utilizing the heating device. The heating device utilizes a rotational reflective cover to modulate a heating direction of a heating source, which expands an area correspondingly irradiated by the heating source and enhances uniformity of heating. Besides, the heating modules can be coupled and controlled by a controlling subsystem so as to respectively irradiate different areas with ranges at least partially intersecting each other, which also improves heating uniformity for heating a large area.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 20, 2021
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chung-Chun Huang, Chih-Peng Chen, Po-Shen Lin
  • Publication number: 20210187686
    Abstract: The present invention discloses a grinding cavity body of multiple vibration sources, in which a plurality of ultrasonic vibration sources are disposed, capable of controlling the multi-directional macroscopic medium flow, making benefits to the vibration medium (the abrasive of the slurry) to enter the fine structure of the workpiece to be processed, and to the abrasive to vibrate itself slightly to enhance the performance of abrasive to the workpiece which needs to be ground.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Po-Shen Lin, Ming-Wei Liu, Chih-Peng Chen, Kuo-Kuang Jen
  • Publication number: 20210187699
    Abstract: The present invention discloses a multi-dimensional vibration grinding cavity body. By adjusting amplitudes (power) and frequencies of the multi-dimensional ultrasonic vibration source, such that the multi-directional macroscopic flow is formed in the cavity body while keeping the vibration medium to have the original characteristics to improve the performance of grinding of slurry.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Po-Shen Lin, Ming-Wei Liu, Chih-Peng Chen, Kuo-Kuang Jen
  • Publication number: 20210125351
    Abstract: A character-tracking system is provided. The system includes a plurality of cameras, a first computing server, a second computing server, and a third computing server. The cameras are configured to capture scene images of a scene with different shooting ranges. The first computing server performs body tracking on a body region in the scene image to generate character data. The third computation server obtains a body region block from each scene image according to the character data for facial recognition to obtain user identity. The first computing server further performs person re-identification on different body regions to link the body regions with its person tag belonging to the same user. The first computing server further represents the linked body regions and their person tags with a corresponding user identity.
    Type: Application
    Filed: February 14, 2020
    Publication date: April 29, 2021
    Inventors: Po-Shen LIN, Shih-Wei WANG, Yi-Yun HSIEH
  • Patent number: 10970860
    Abstract: A character-tracking system is provided. The system includes a plurality of cameras, a first computing server, a second computing server, and a third computing server. The cameras are configured to capture scene images of a scene with different shooting ranges. The first computing server performs body tracking on a body region in the scene image to generate character data. The third computation server obtains a body region block from each scene image according to the character data for facial recognition to obtain user identity. The first computing server further performs person re-identification on different body regions to link the body regions with its person tag belonging to the same user. The first computing server further represents the linked body regions and their person tags with a corresponding user identity.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 6, 2021
    Assignee: WISTRON CORP.
    Inventors: Po-Shen Lin, Shih-Wei Wang, Yi-Yun Hsieh