Abstract: The present disclosure provides a method for aligning a master oscillator power amplifier (MOPA) system. The method includes ramping up a pumping power input into a laser amplifier chain of the MOPA system until the pumping power input reaches an operational pumping power input level; adjusting a seed laser power output of a seed laser of the MOPA system until the seed laser power output is at a first level below an operational seed laser power output level; and performing a first optical alignment process to the MOPA system while the pumping power input is at the operational pumping power input level, the seed laser power output is at the first level, and the MOPA system reaches a steady operational thermal state.

Abstract: The present invention discloses a mold core for manufacturing a container closure comprising a plurality of slides, a sleeve placed over the plurality of slides, a slide seat on which the plurality of slides are mounted, and a cam device arranged inside a space defined by the plurality of slides. The plurality of slides comprise a plurality of first independent slides and a plurality of second independent slides, wherein each of the first independent slides and each of the second independent slides are configured to be individually mounted on and individually detached from the slide seat; and wherein axial movement of the sleeve relative to the first independent slides and the second independent slides effects application of radial force onto the first independent slides and the second independent slides successively, so as to cause successive inward movement of the first independent slides and of the second independent slides within the sleeve.

Abstract: The present invention discloses a mold core for manufacturing a container closure comprising a plurality of slides, a sleeve placed over the plurality of slides, a slide seat on which the plurality of slides are mounted, and a cam device arranged inside a space defined by the plurality of slides. The plurality of slides comprise a plurality of first independent slides and a plurality of second independent slides, wherein each of the first independent slides and each of the second independent slides are configured to be individually mounted on and individually detached from the slide seat; and wherein axial movement of the sleeve relative to the first independent slides and the second independent slides effects application of radial force onto the first independent slides and the second independent slides successively, so as to cause successive inward movement of the first independent slides and of the second independent slides within the sleeve.

Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.

Abstract: A system comprising communication logic capable of receiving data signals from a network. The signals comprise both erasure error and random error. The system also comprises processing logic coupled to the communication logic and adapted to partition parity check bytes of the received signals into a first portion and a second portion. The processing logic uses the first portion for random error correction and the second portion for erasure error correction.

Abstract: Methods and apparatus to perform erasure forecasting in communication systems are disclosed. A disclosed example apparatus comprises a forward error correction (FEC) decoder to decode a first codeword and to provide a first error indication for the first codeword, an erasure forecaster to make an erasure decision for a second codeword based on the first error indication, and an erasure forecasting state table including a first field associated with first interleaved data and a second field associated with second interleaved data, the second codeword containing a first element from the first interleaved data and a second element from the second interleaved data.

Abstract: An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and registers) works for variable P,D,m. This is achieved by decomposing the (P,D,m) interleaver into a concatenation of a multiplexed interleaver (implemented with A+1 memory locations), followed by a block interleaver (implemented with 2P memory locations). In many applications, these 2P memory locations can be treated as part of the memory for controlling the data flow of the system.

Abstract: An efficient way to generate the address sequence for the RAM implementation of Forney's (P, D, m) interleavers requires only A+1+2P memory locations, which is close to the theoretical minimum. Here A is the average delay of the symbols through the interleaver. The address generation circuit (with simple adders and registers) works for variable P,D,m. This is achieved by decomposing the (P,D,m) interleaver into a concatenation of a multiplexed interleaver (implemented with A+1 memory locations), followed by a block interleaver (implemented with 2P memory locations). In many applications, these 2P memory locations can be treated as part of the memory for controlling the data flow of the system.

Abstract: The present invention provides a system for mitigating impulse noise effects in a digital data transmission system, particularly in a DSL-based communications system (300), by optimizing error correction systems with an erasure forecasting scheme. Within the communications system, encoding and structuring constructs form and permute data transmission units for transmission in a deterministic manner (i.e., having known, fixed characteristics). Once data transmission units have been received over a transmission channel, de-structuring and decoding constructs inversely permute and decode those data transmission units, according to the deterministic manner. Data decoding is monitored (302), and the occurrence of an impulse noise event in the transmission channel is identified (304). A first data transmission unit affected by the impulse noise event is decoded (306).

Abstract: This invention represents a method of using cryptography with biometric verification on security authentication. The present invention relates to secure transmission of data or confidential information and, in particular, to cryptography technology that prevents the multiple passwords of keys lengthy, inconvenient and hard to be remembered or hidden. The method is used to perform security authentication by utilizing live biometric feature, which is non-transferable and unique among all humans, and operating the asymmetric key of cryptography technique for collation. Therefore, in the present invention, the method is capable of providing cryptography technology in conjunction with the biometric authorization to prevent that people don't like to carry private keys and using a single key only to perform authentication will reveal privacy or private information.

Abstract: A method uses a hybrid neural network including a self organizing mapping neural network (SOM NN) and a, back-propagation neural network (BP NN) for color identification. In the method the red, green and blue (RGB) of color samples are input as features of training samples and are automatically classified by way of SOM NN. Afterwards, the outcomes of SOM NN are respectively delivered to various BP NN for further learning; and the map relationship of the input and the output defines the X,Y, Z corresponding the x, y and z values of a coordinate system of the standard color samples of RGB and IT8. By way of the above learning structure, a non-linear model of color identification can be set up. After color samples are self organized and classified by SOM NN network, data can be categorized in clusters as a result of characteristic difference thereof.

Abstract: This invention represents a Web-based biometric authorization apparatus. The present invention relates to live biometric characteristics which are captured by a biometric capture device and, in particular, to the Biometric Identification Record (BIR) and personal information which are stored in a digitized data storage apparatus. It is therefore an object of the present invention to provide the further data process which includes compression and decompression function, encryption and decryption function, and to provide the BIR process which relates to calculation, collation and verification as a secured mechanism. The apparatus is operatively coupled to a remote site so as to establish an Internet communication link through wired or wireless communications. Therefore, the biometric verification is performed with peripheral devices such as POS terminals, ATM terminals, credit card reader, access control or other control mechanism.

Abstract: This invention represents a portable biometric verification and storage device. The portable device performs the biometric characteristics recognition or verification for providing high security of personal identification by collating digital Biometric Identification Record (BIR) stored in the device and personal activated biometric characteristics. The Biometric Identification Record (BIR) includes a memory for storing at least one or more personal biometric characteristics database and for storing at least one or more ID of each person and personal information in a portable biometric verification and storage device.

Abstract: Improved approaches to provide flexibility in setting user data rates and managing delay in data transmission systems using a superframe structure and Time Division Duplexing (TDD) are disclosed. These improved approaches operate to provide intelligent insertion of dummy words (bits or bites) into a data stream to be transmitted. By inserting the dummy words, the invention is able to render codewords, symbols and superframes independent from user data rates. As a result, a wide range of user data rates are available in data transmission systems using a superframe and TDD.

Abstract: This invention represents a method of bank card and credit card with fingerprint authentication for identifying whether a user is a registered owner of the card. The reference fingerprint data will be digitized and stored in an IC chip or stored on a magnetic strip of a bank card and a credit card. Therefore, this invention can identify the correct user of the bank card or the credit card by collating the measured fingerprint data with the reference fingerprint data via a fingerprint ATM terminal or a fingerprint reading device of the credit card. It could prevent the illegal use of these cards and heavy financial problems of issuing banks.

Abstract: A method of coordinating very high speed bi-directional data transmissions between a central unit and a plurality of remote units over distinct twisted pair transmission lines that share a binder is described. Specifically, periodic synchronized upstream and downstream communication periods are provided that do not overlap with one another. The upstream and downstream communication periods for all of the wires that share a binder are synchronized. With this arrangement, all of the very high speed transmissions within the same binder are synchronized and time division duplexed such that downstream communications are not transmitted at times that overlap with the transmission of upstream communications. In some embodiments, quiet periods are provided to separate the upstream and downstream communication periods. The described invention may be used in conjunction with a wide variety of modulation schemes, including both multi-carrier and single carrier transmission schemes.

Abstract: A convolutional interleaving process which utilizes an addressing scheme that enables the amount of memory to be used in the convolutional interleaving process to be reduced is disclosed. A stream of data is convolutionally interleaved at a designated interleaving depth and a designated interleaving block length such that a first symbol in a designated block has an associated predetermined delay and each subsequent symbol in the designated block has a delay equal to more than its predecessor symbol. A plurality of delay related arrays, as well as an initial value array, a lower limit array, and an upper limit array, are calculated in order to define interleaving orbits. The convolutional interleaving process is accomplished by a convolutional interleaver which is arranged to take an incoming stream of data and output an interleaved stream of bits which is conceptually partitioned into blocks. A convolutional deinterleaving process, which is similar to the convolutional interleaving process is also disclosed.

Abstract: A method of coordinating very high speed bi-directional data transmissions between a central unit and a plurality of remote units over distinct twisted pair transmission lines that share a binder is described. Specifically, periodic synchronized upstream and downstream communication periods are provided that do not overlap with one another. The upstream and downstream communication periods for all of the wires that share a binder are synchronized. With this arrangement, all of the very high speed transmissions within the same binder are synchronized and time division duplexed such that downstream communications are not transmitted at times that overlap with the transmission of upstream communications. In some embodiments, quiet periods are provided to separate the upstream and downstream communication periods. The described invention may be used in conjunction with a wide variety of modulation schemes, including both multi-carrier and single carrier transmission schemes.

Abstract: A transmission system using multicarrier modulation applies FECC (forward error correcting code) coding and codeword interleaving differently to input signals from a plurality of different data channels to produce encoded data signals having different reliabilities and different coding delays. Bits of encoded data signals having relatively less delay are allocated to carriers that are subject to relatively more attenuation and/or channel noise, and hence that are allocated fewer bits for transmission in each symbol period, to reduce the effects of impulse noise. The data channels can comprise video, data, and control channels transmitted on an ADSL (asymmetric digital subscriber line) two-wire telephone line.