Abstract: A power sum computation unit for a Reed-Solomon decoder having r redundant symbols and in which a code word, R, has a first plurality (n) of symbols, each symbol having a plurality (m) of bits, including multiplier unit for multiplying in parallel M symbols by powers of a finite field element, .alpha., to obtain the power sums ##EQU2## The multiplier unit includes M multipliers for multiplying M symbols by powers of alpha, and memory delay including a latch, a random access memory, and a flipflop store symbols and sequentially provide M symbols to the multiplier unit. Exclusive OR gate selectively connects products from the multiplier unit and data input words to the memory delay. A counter is provided for the random access memory with the counter having a modulo number equal to one less than r/M, and the random access memory having a depth equal to one less than r/M.

Abstract: Sequential encoding of Reed-Solomon codes using a discrete time delay line, a single adder, and a single multiplier provides efficient encoding of Reed-Solomon codes with or without interleaving. The encoder utilizes a clock whose rate is r times the symbol rate where r is the redundancy of the code. The finite field operations are performed in a sequential manner requiring only one finite field multiplier and one finite field adder. All memory elements are consolidated into a discrete time delay line which can be implemented with a random access memory. The encoder can be easily reconfigured for changes in generator polynomial of the code, the amount of redundancy, and interleaving depth.

Abstract: A structure and a method are provided for fast-decoding a Huffman code using means for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, and means for removing from the Huffman codeword the number of leading 1's recognized. In one embodiment, both JPEG Huffman code AC and DC tables are stored in a random access memory (RAM). In that embodiment, to access the AC code tables, an address is formed by the number of leading 1's recognized and the portion of Huffman code with the number of leading 1's recognized removed. To access the DC code tables, an address is formed by a predetermined code pattern and the Huffman codeword.

Abstract: A method and a structure are provided for decoding Huffman codes using a random access memory having a size less than twice the total number of codewords decodable. Under this method, the number of leading 1's in a Huffman codeword and the bits of the Huftman code word other than the leading 1's ("remainder") are combined to form an address into the random access memory. Using the fact that, for a given number of leading 1's in a Huffman code, the possible remainder of the Huffman code is no longer than a predetermined number of bits, the size of the random access memory necessary for decoding such Huffman codes can be made optimally small.

Abstract: A structure and a method are provided for fast-decoding a Huffman code using a leading 1's detector for recognizing the number of leading 1's in the Huffman codeword up to a predetermined maximum, so as to provide a class number in accordance with the number of leading 1's recognized, a first logic circuit for providing a "remainder" by removing from the Huffman codeword a number of bits in accordance with the class number, and a second logic circuit for recognizing a special class. In one embodiment, decoding is accomplished by accessing a storage device using an address formed by a table number, a subclass number derived from the class number and all of the bits in the remainder except the least significant bit.

Abstract: A Reed-Solomon decoder is implemented in systolic arrays wherein clock and control information propagate serially with the data. Progressive loss of coherence in such arrays is compensated by a folded array structure symmetrized in clock control whereby coherence is progressively re-established at the output of each such array.

Abstract: Transmitting and receiving apparatus for transmitting data which includes a purged extended Golay (22,7) code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords contain error correction bits and are preferably transmitted as balanced codewords. When the receiver decodes the original digital data, improved tracking and acquisition of the transmitted data is achieved.

Abstract: Multiplication of two mq-bit bytes (in GF2.sup.mq) is reduced modulus an irreducible polynomial in GF2.sup.m of degree q to multiplication among two sets of q m bit bytes (in GF2.sup.m) in order to simplify hardware and reduce costs, by distributing the computation among a small number of programmable read only memories (PROMs) and adders.

Abstract: By translating in accordance with a predetermined permutation the virtual check locations of a virtual message re-encoder, plural erroneous symbols (up to a certain limit) occurring in any pattern in a received codeword may be trapped simultaneously in virtual check locations. By simply adding to them the corresponding virtual check symbols computed by the virtual message re-encoder, the correct codeword is easily obtained. In one embodiment of the invention, any pattern of two erroneous symbols in a codeword of length n may be trapped in this manner by defining the predetermined permutation in accordance with a modulus n cyclic difference set. In this embodiment, for an RS(31, 25) code, the cyclic difference set (0, 4, 10, 23, 24, 26) may be used as the predetermined permutation.

Abstract: To each bit time of a data block, there is associated a counter which is incremented or decremented in accord with the congruence or non-congruence of the c bit sequence associated with the respective counter (for example, the first bit of the c bit sequence). The counters are initialized to an optimum non-zero value and after receiving a number of blocks of data, each containing one sync symbol, the synchronization is determined from the relative content of the counters.

Abstract: An improved method and apparatus for interleaving block codes exploits helical symmetry whereby correspondingly positioned code symbols of code words of length n interleaved to depth i, i<n, are separated on the channel by .alpha.i+.beta. symbol intervals where 1+.gamma..gtoreq.i is averaged over the i correspondingly positioned symbols and .alpha.and .vertline..beta..vertline. are integers >1. The requirement for synchrony is reduced to a period counted modulo n instead of mod (n.times.i). For the case i=n-1, the total interleaving delay is reduced to 2(n-1)n and phase dependence of burst error onset is minimized. The performance of the de-interleaver is enhanced through a pseudo fade detector implemented by creating erasures prior to decoding, at certain positions for codewords subsequent to confirmed error. Synchronization of interleaver and de-interleaver is accomplished in apparatus which inspects all c contiguous bit patterns corresponding to a c bit synch symbol.