Patents by Inventor Po-Wen Su

Po-Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11374127
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20220175291
    Abstract: A smart clothes for sensing heart physiological activities and lung respiratory conditions is provided, the smart clothes utilizes conductive connecting elements for being externally connected to a control module, such that the control module can be expanded or upgraded according to functional requirements. Further in the smart clothes, sensing elements and signal transmission wires are made of conductive fabric. As the conductive fabric sensing elements and signal transmission wires are well attached to a clothing body of the smart clothing, the sensing elements can be better adhered to human skin, and thereby sensing accuracy is improved.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 9, 2022
    Inventors: SHUENN-YUH LEE, Yi-Wen Hung, PO-HAN SU
  • Publication number: 20220171446
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, an unloaded component is detected. The unloaded component remains undetected upon completion of a boot process of the computing device. Thereafter, a power budget allocated to the unloaded component is determined. The power budget may be based on the thermal design power (TDP) of the computing device. Based on the power budget, a power configuration of the CPU is changed from a default power level to a high-performance power level, wherein the default power level corresponds to the TDP of the computing device and the high-performance power level is a power level above the default power level and upto a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: June 2, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Yen Tang Chang, Chao Wen Cheng, Chien Chen Su, Po Ying Chih
  • Publication number: 20220147127
    Abstract: Techniques for allocating power budget to a central processing unit (CPU) of a computing device are described. According to an example of the present subject matter, a CPU is operated at default power level corresponding to a thermal design power (TDP) of the computing device. Thereafter, an unused power of the computing device is determined at run-time. The unused power is a difference between an allocated power budget of the component and current power consumption of the component, wherein the allocated power budget is an amount of power allocated to the component based on the TDP of the computing device. Based on the unused power the CPU is operated at a high-performance power level. The high-performance power level is a power level above the default power and up to a maximum power level of the CPU.
    Type: Application
    Filed: July 31, 2019
    Publication date: May 12, 2022
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po Ying Chih, Chao Wen Cheng, Yen Tang Chang, Wei Chieh Liao, Yu Fan Chen, Chien Chen Su
  • Publication number: 20220077300
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 10, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Publication number: 20220069102
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: March 3, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11205710
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: December 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Patent number: 11205705
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: December 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Publication number: 20210249529
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: August 12, 2021
    Inventors: Po-Wen Su, Ming-Hua Chang, Shui-Yen Lu
  • Publication number: 20200144387
    Abstract: A gate structure includes a substrate divided into an N-type transistor region and a P-type transistor region. An interlayer dielectric covers the substrate. A first trench is embedded in the interlayer dielectric within the N-type transistor region. A first gate electrode having a bullet-shaped profile is disposed in the first trench. A gate dielectric contacts the first trench. An N-type work function layer is disposed between the gate dielectric layer and the first gate electrode. A second trench is embedded in the interlayer dielectric within the P-type transistor region. A second gate electrode having a first mushroom-shaped profile is disposed in the second trench. The gate dielectric layer contacts the second trench. The N-type work function layer is disposed between the gate dielectric layer and the second gate electrode. A first P-type work function layer is disposed between the gate dielectric layer and the N-type work function layer.
    Type: Application
    Filed: November 29, 2018
    Publication date: May 7, 2020
    Inventors: Jie-Ning Yang, Wen-Tsung Chang, Po-Wen Su, Kuan-Ying Lai, Bo-Yu Su, Chun-Mao Chiou, Yao-Jhan Wang
  • Patent number: 10522652
    Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Po-Wen Su, Chih-Wei Lin, Wei-Chih Lai, Tai-Yen Lin
  • Patent number: 10505007
    Abstract: A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Wen-Yen Huang, Kuan-Ying Lai, Shui-Yen Lu
  • Patent number: 10483158
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Publication number: 20190214480
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Patent number: 10283616
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Publication number: 20190122920
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10199260
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10177245
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Patent number: 10043882
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen