Patents by Inventor Po-Wen Su

Po-Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200363773
    Abstract: The present disclosure provides a protection casing assembly for a wearable device. The protection casing assembly includes a main case and a frame. The main case has a first accommodation space and configured to allow a wearable device to be disposed detachably. When the wearable device is disposed in the first accommodation space, the wearable device and the main case define a second accommodation space adjacent to at a device surface of the wearable device. The frame is detachably disposed in the second accommodation space.
    Type: Application
    Filed: October 2, 2019
    Publication date: November 19, 2020
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Publication number: 20200357922
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20200352045
    Abstract: The present disclosure provides a foldable apparatus for receiving a foldable device. The foldable apparatus includes a casing for receiving the foldable device. The casing includes a body and a bending zone. The body is for providing an accommodation to the foldable device. The bending zone is for folding the body from an unfolded position to a folded position. The bending zone includes a stress relaxation structure for retaining the body in the folded position and reversing the body to the unfolded position.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Inventors: CHING-FU WANG, SHENG-CHE SU, PO-WEN HSIAO, CHIA-HO LIN
  • Patent number: 10727350
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 10522652
    Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Po-Wen Su, Chih-Wei Lin, Wei-Chih Lai, Tai-Yen Lin
  • Patent number: 10505007
    Abstract: A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Wen-Yen Huang, Kuan-Ying Lai, Shui-Yen Lu
  • Patent number: 10483158
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10283616
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: May 7, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Publication number: 20190122920
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10199260
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10177245
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Patent number: 10043882
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Patent number: 10026827
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Grant
    Filed: April 10, 2016
    Date of Patent: July 17, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Publication number: 20180151685
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20180061963
    Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.
    Type: Application
    Filed: August 30, 2016
    Publication date: March 1, 2018
    Inventors: Wen-Chien Hsieh, En-Chiuan Liou, Chih-Wei Yang, Yu-Cheng Tung, Po-Wen Su
  • Patent number: 9899491
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20180033874
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Application
    Filed: July 26, 2017
    Publication date: February 1, 2018
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Publication number: 20170330952
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
    Type: Application
    Filed: June 15, 2016
    Publication date: November 16, 2017
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Publication number: 20170294523
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
    Type: Application
    Filed: April 10, 2016
    Publication date: October 12, 2017
    Inventors: Zhen Wu, Chiu-Hsien Yeh, Po-Wen Su, Kuan-Ying Lai
  • Patent number: D906892
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 5, 2021
    Assignee: Gogoro Inc.
    Inventors: Hsun-Hsueh Lin, Ting-Ping Ku, Meng Yuan Wu, Shih-Yuan Lin, Hsin-Wen Su, Po-Chang Yeh, Liang-Yi Hsu