Patents by Inventor Po-Wen Su

Po-Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9443741
    Abstract: An etching method includes forming a high density structure and a low density structure on a substrate. A first material layer is formed to cover both structures. Part of the low density structure is exposed through the first material layer. A second material layer is formed to cover the first material layer. The second material layer is etched to remove the second material layer on the high density structure and part of the second material layer on the low density structure. The first material layer on the high density structure and the second material layer on the low density structure are simultaneously etched. The first material layer is etched to expose a first portion of the high density structure and a second portion of the low density structure. Finally, the first portion and the second portion are removed.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 13, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhi-Jian Wang, Cheng-Chang Wu, Hsin-Yu Hsieh, Shui-Yen Lu
  • Patent number: 9117904
    Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
  • Patent number: 9117909
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 25, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20150137197
    Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.
    Type: Application
    Filed: January 28, 2015
    Publication date: May 21, 2015
    Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
  • Patent number: 8975673
    Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: March 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen
  • Publication number: 20140367798
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20140308761
    Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
    Type: Application
    Filed: April 15, 2013
    Publication date: October 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20140306272
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Application
    Filed: April 16, 2013
    Publication date: October 16, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Patent number: 8853015
    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: October 7, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20130270613
    Abstract: A method of trimming spacers includes etching a silicon oxide spacer when forming an outmost spacer, so that a silicon carbon nitride spacer contacting the gate electrode exposes an area. The exposure area of the silicon carbon nitride spacer can then be partly removed by phosphate acid. At the end of the semiconductor process, at least part of the top surface of the silicon carbon nitride spacer will be lower than the top surface of a gate electrode.
    Type: Application
    Filed: April 16, 2012
    Publication date: October 17, 2013
    Inventors: Shyan-Liang Chou, Tsung-Min Kuo, Po-Wen Su, Chun-Mao Chiou, Feng-Mou Chen