Patents by Inventor Po-Yu Chen

Po-Yu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250232105
    Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein he first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.
    Type: Application
    Filed: April 4, 2025
    Publication date: July 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yi Lin, Fong-yuan Chang, Po-Yu Chen, Po-Hsiang Huang, Chih-Wei Chang, Jyh Chwen Frank Lee
  • Patent number: 12359502
    Abstract: A ladder rope retaining device includes a support base, a rotating base, and an elastic positioning member. The support base has a bottom wall and two opposite straight walls connected with the bottom wall and each having a pivot trough. The rotating base includes a pivot pivotally disposed in the pivot troughs, and a ladder rope retaining portion formed on the pivot. The pivot has a plurality of positioning recesses arranged in an equally-spaced manner. The elastic positioning member is disposed to one of the straight walls of the support base and elastically engaged with one of the positioning recesses of the pivot. Thus, when the rotating base is rotated relative to the support base, the positioning recesses are alternately engaged with and disengaged from the elastic positioning member to generate a better operating feel.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 15, 2025
    Assignee: SHEEN WORLD TECHNOLOGY CORPORATION
    Inventor: Po-Yu Chen
  • Publication number: 20250210610
    Abstract: A package structure and a method for forming a package structure are provided. The package structure includes a chip-containing structure bonded to a redistribution structure through multiple first solder bumps. The package structure also includes a memory-containing structure bonded to an interposer chip. The interposer chip is bonded to the redistribution structure through multiple second solder bumps. The package structure further includes a substrate, and the redistribution structure is over the substrate.
    Type: Application
    Filed: April 25, 2024
    Publication date: June 26, 2025
    Inventors: Po-Yu Chen, Yu Hsiang Chen
  • Patent number: 12336108
    Abstract: The present application provides a learning method for plug-in depth including steps of: (a) utilizing a robot arm to take an electronic component with a plurality of pins; (b) utilizing a first visual device to identify a pin distance; (c) utilizing a second visual device to identify a hole distance; (d) inserting the plurality of pins into the corresponding plurality of holes with a predetermined depth according to the pin distance and the hole distance; (e) determining whether the plurality of pins are inserted into the plurality of holes, performing step (f) when the determination result is satisfied, and performing step (g) when the determination result is not satisfied; (f) recording the predetermined depth and performing the step (a) again; (g) calibrating the predetermined depth and performing the step (a) again; and (h) completing the learning of the plug-in depth after the step (f) is performed multiple times successively.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: June 17, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Jian-Jang Lai, Po-Yu Chen, Chien-Ta Lin
  • Patent number: 12322874
    Abstract: An antenna module including a substrate, a main antenna and a parasitic antenna is provided. The substrate has a ground. The main antenna is disposed on the substrate. The main antenna includes a first irradiating portion, a feeding portion and a first grounding portion, and the first grounding portion is connected to the ground. The parasitic antenna is disposed on the substrate. The parasitic antenna includes a second irradiating portion and a second grounding portion, and the second grounding portion is connected to the ground. An extending direction of the first irradiating portion and an extending direction of at least a part of the second irradiating portion are perpendicular to each other.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: June 3, 2025
    Assignee: Wistron Corporation
    Inventors: Cheng-Chieh Yang, Po Yu Chen, Sheng Hui Yang
  • Patent number: 12299369
    Abstract: A method includes: receiving a layout of an integrated circuit; identifying, based on the layout, at least a first net and at least a second net, wherein the first net extends through the integrated circuit along a vertical direction, and the second net terminates at a middle portion of the integrated circuit along the vertical direction; dividing the integrated circuit into a plurality of grid units, wherein the first net is constituted by a first subset of the plurality of grid units, and the second net is constituted by a second subset of the plurality of grid units; estimating a first thermal conductivity of each of the first subsets of grid units; estimating a second thermal conductivity of each of the second subsets of grid units; and estimating an equivalent thermal conductivity of the integrated circuit based on combining the first thermal conductivity and the second thermal conductivity.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yi Lin, Fong-yuan Chang, Po-Yu Chen, Po-Hsiang Huang, Chih-Wei Chang, Jyh Chwen Frank Lee
  • Publication number: 20250140642
    Abstract: A thermoelectric cooler (TEC) is positioned to move heat away from a hot spot on a semiconductor chip and toward a dielectric substrate. This approach to thermal management is particularly effective when used in conjunction with a buried rail and back side power delivery. The TEC may be in a layer that contains solder connections be between two device layers an IC package. Alternatively, the TEC may be in a metal interconnect structure over the semiconductor substrate such as in a passivation stack at the top of the metal interconnect structure. TECs at either of these locations may be formed by wafer-level processing.
    Type: Application
    Filed: March 6, 2024
    Publication date: May 1, 2025
    Inventors: Cheng-Ming Lin, Che Chi Shih, Wei-Yen Woon, Szuya Liao, Isha Datye, Sam Vaziri, Po-Yu Chen, Cheng Hung Wu, Wei-Pin Changchien, Xinyu Bao
  • Publication number: 20250096185
    Abstract: A semiconductor structure can include a first substrate having a frontside and a backside opposite the frontside. The semiconductor structure can include devices on the frontside. The semiconductor structure can include first interconnect structures on the frontside and coupled to the devices. The semiconductor structure can include a heat distribution layer on the frontside and electrically isolated from the first interconnect structures, where the heat distribution layer includes a thermally conductive material. The semiconductor structure can include a second substrate coupled to the first substrate on the frontside. The semiconductor structure can include second interconnect structures on the backside and coupled to the devices.
    Type: Application
    Filed: September 18, 2023
    Publication date: March 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Chen, Cheng Hung Wu, Hui-Ling Lin, Yu Hsiang Chen
  • Publication number: 20250068423
    Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 27, 2025
    Applicant: Intel Corporation
    Inventors: Jorge Eduardo Parra Osorio, Jiasheng Chen, Supratim Pal, Vasanth Ranganathan, Guei-Yuan Lueh, James Valerio, Pradeep Golconda, Brent Schwartz, Fangwen Fu, Sabareesh Ganapathy, Peter Caday, Wei-Yu Chen, Po-Yu Chen, Timothy Bauer, Maxim Kazakov, Stanley Gambarin, Samir Pandya
  • Patent number: 12228657
    Abstract: A wireless device includes a satellite receiver to receive data from multiple satellites. The wireless device also includes processing circuitry and memory. The memory stores one or more neural network models. The processing circuitry is operative to identify a neural network model that has been trained to adapt to a region in which the wireless device operates, classify satellite raw measurements from each satellite at a given time into a corresponding quality level using the neural network model, and identify satellite raw measurements with a quality level higher than a threshold. The location of the wireless device is calculated using the identified satellite raw measurements.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: February 18, 2025
    Assignee: MediaTek Inc.
    Inventors: Po-Yu Chen, Hao Chen, Tsung-Yu Chiou
  • Publication number: 20250040219
    Abstract: A semiconductor device includes an isolation structure in a substrate. The semiconductor device further includes a gate structure over a first region of the substrate, wherein the isolation structure surrounds the first region, the gate structure comprising a first section and a second section. The semiconductor device further includes a conductive field plate over the substrate, the conductive field plate extending between the first section and the second section and overlapping an edge of the first region, wherein the conductive field plate comprises a dielectric layer having a variable thickness. The semiconductor device further includes a first well in the substrate, wherein the first well overlaps the edge of the first region, and the first well extends underneath the isolation structure, and the conductive field plate extends beyond an outer-most edge of the first well.
    Type: Application
    Filed: October 10, 2024
    Publication date: January 30, 2025
    Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN
  • Patent number: 12150574
    Abstract: A knife rack includes a box body having a bottom, a plurality of peripheral walls surrounding the bottom, an accommodating space surrounded by the peripheral walls and the bottom and an opening provided where the accommodating space communicates with the outside, a top cover covering the opening and provided with a plurality of long slotted holes, and a plurality of round balls set within the accommodating space of the box body and used as a support structure for supporting knifes. The point-like contact between the round balls and the blades of stored knives can greatly reduce the contact area between the round balls and the blades, and the gaps between the round balls are conducive to air circulation.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: November 26, 2024
    Assignee: DOTS TECHNOLOGY INC.
    Inventors: Race Wu, Po-Chun Chuang, Po-Yu Chen
  • Publication number: 20240349471
    Abstract: The present application provides a learning method for plug-in depth including steps of: (a) utilizing a robot arm to take an electronic component with a plurality of pins; (b) utilizing a first visual device to identify a pin distance; (c) utilizing a second visual device to identify a hole distance; (d) inserting the plurality of pins into the corresponding plurality of holes with a predetermined depth according to the pin distance and the hole distance; (e) determining whether the plurality of pins are inserted into the plurality of holes, performing step (f) when the determination result is satisfied, and performing step (g) when the determination result is not satisfied; (f) recording the predetermined depth and performing the step (a) again; (g) calibrating the predetermined depth and performing the step (a) again; and (h) completing the learning of the plug-in depth after the step (f) is performed multiple times successively.
    Type: Application
    Filed: July 13, 2023
    Publication date: October 17, 2024
    Inventors: Jian-Jang Lai, Po-Yu Chen, Chien-Ta Lin
  • Patent number: 12119384
    Abstract: A semiconductor device includes an isolation structure in a substrate; and a gate structure over an active region of the substrate. The isolation structure surrounds the active region. The gate structure includes a first section parallel to a second section. The semiconductor device further includes a conductive field plate extending between the first section and the second section and overlapping an edge of the active region. A portion of the conductive field plate extends beyond the edge of the active region, The conductive field plate includes a dielectric layer having a first portion and a second portion, and the first portion is thicker than the second portion. The semiconductor device includes a first well overlapping the edge of the active region. The first well extends underneath the isolation structure. The conductive field plate extends beyond an outer-most edge of the first well.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen
  • Patent number: 12107343
    Abstract: An antenna structure includes a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, and a switch circuit. The feeding radiation element has a feeding point. The second radiation element is coupled through the first radiation element to the feeding radiation element. The third radiation element is coupled to the second radiation element. The fourth radiation element is coupled to the second radiation element. The fourth radiation element and the third radiation element extend in different directions. The fifth radiation element has a tuning point, and is coupled to the feeding radiation element. The feeding radiation element is disposed between the first radiation element and the fifth radiation element. The switch circuit selectively couples the tuning point to a ground voltage.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: October 1, 2024
    Assignee: WISTRON CORP.
    Inventors: Cheng-Chieh Yang, Chih-Ming Chen, Po-Yu Chen
  • Publication number: 20240317511
    Abstract: An automatic pick-and-place system is provided, including a feeding device, a visual pattern formed on a fixed part of the feeding device, a manipulator, and a processing unit. An electronic component can be held between the fixed part and a gripping part of the feeding device. A visual module on the manipulator captures an image of the visual pattern, and the processing unit calculates the coordinate value of the electronic component. Thus, the manipulator can move to the target position and pick up the electronic element according to the coordinate value.
    Type: Application
    Filed: September 1, 2023
    Publication date: September 26, 2024
    Inventors: Chien-Ta LIN, Jie-Shiou TSAI, Po-Yu CHEN, Jian-Jang LAI
  • Publication number: 20240268586
    Abstract: A knife rack includes a box body having a bottom, a plurality of peripheral walls surrounding the bottom, an accommodating space surrounded by the peripheral walls and the bottom and an opening provided where the accommodating space communicates with the outside, a top cover covering the opening and provided with a plurality of long slotted holes, and a plurality of round balls set within the accommodating space of the box body and used as a support structure for supporting knifes. The point-like contact between the round balls and the blades of stored knives can greatly reduce the contact area between the round balls and the blades, and the gaps between the round balls are conducive to air circulation.
    Type: Application
    Filed: November 15, 2023
    Publication date: August 15, 2024
    Applicant: DOTS TECHNOLOGY INC.
    Inventors: Race Wu, Po-Chun Chuang, Po-Yu Chen
  • Patent number: 12047222
    Abstract: A radio frequency (RF) communication assembly includes an RF communication circuit and a compensator apparatus. The compensator apparatus receives an input including an I-component of a pre-compensated signal, a Q-component of the pre-compensated signal, and encoded operating conditions of the RF communication circuit. The RF communication circuit includes RF circuit components causing signal impairments. The compensator apparatus perform neural network computing on the input, and the RF communication assembly generates a compensated output signal that compensates for at least a portion of the signal impairments.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: July 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Po-Yu Chen, Yen-Liang Chen, Chi-Tsan Chen, Chao-Wei Wang
  • Publication number: 20240233990
    Abstract: A non-oriented electrical steel sheet with characteristics of high permeability, high magnetic flux, and low iron loss and a manufacturing method thereof are provided. The non-oriented electrical steel sheet includes an electrical steel, wherein the electrical steel includes the following compositions of: an amount of 0.005 wt. % or less of carbon, an amount of 0.005 wt. % or less of nitrogen, an amount of 0.005 wt. % or less of sulfur, an amount of 0.05 wt. % or less of phosphorus, an amount of 1.0 to 2.5 wt. % of silicon, an amount of 0.1 to 0.8 wt. % of aluminum, an amount of 0.1 to 0.8 wt. % of manganese, an amount of 0.01 to 0.10 wt. % of antimony and the balance of iron and other unavoidable impurities, wherein the electrical steel meets the following relationship: 20?10*silicon content+11*aluminum content+6*manganese content?30.
    Type: Application
    Filed: November 30, 2023
    Publication date: July 11, 2024
    Inventors: Po-yu CHEN, I-ching HSIAO, Ming-chin TSAI, Hsin-yi LEE, Lin HSU
  • Publication number: 20240222866
    Abstract: An antenna module including a substrate, a main antenna and a parasitic antenna is provided. The substrate has a ground. The main antenna is disposed on the substrate. The main antenna includes a first irradiating portion, a feeding portion and a first grounding portion, and the first grounding portion is connected to the ground. The parasitic antenna is disposed on the substrate. The parasitic antenna includes a second irradiating portion and a second grounding portion, and the second grounding portion is connected to the ground. An extending direction of the first irradiating portion and an extending direction of at least a part of the second irradiating portion are perpendicular to each other.
    Type: Application
    Filed: March 8, 2023
    Publication date: July 4, 2024
    Applicant: Wistron Corporation
    Inventors: Cheng-Chieh Yang, Po Yu Chen, Sheng Hui Yang