Abstract: An image sensor includes a group of sensor units and a color filter layer disposed within the group of sensor units. The image sensor further includes a dielectric structure and a plurality of polarization splitters disposed corresponding to the color filter layer. Each of the plurality of polarization splitters has a first meta element extending in a first direction from top view and a second meta element extending in a second direction from top view. The second direction is perpendicular to the first direction.

Abstract: At least some embodiments of the present disclosure relate to an electronic package structure. The electronic package structure includes an electronic structure, a wiring structure disposed over the electronic structure, a bonding element connecting the wiring structure and the electronic structure, and a reinforcement element attached to the wiring structure. An elevation difference between a highest point and a lowest point of a surface of the wiring structure facing the electronic structure is less than a height of the bonding element.

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: An image sensor includes a photoelectric conversion layer, a plurality of deep trench isolations, a first color filter, a first deflector, and a covering layer. The photoelectric conversion layer includes a first photodiode and a second photodiode. The deep trench isolations separate the first photodiode and the second photodiode, in which a pixel dimension is determined by a distance between two adjacent deep trench isolations. The first color filter is disposed on the first photodiode and the second photodiode. The first deflector is disposed on the first color filter. The covering layer covers and surrounds the first deflector. A refractive index of the covering layer is greater than a refractive index of the first deflector, and a difference value between the refractive index of the covering layer and the refractive index of the first deflector is in a range from 0.15 to 0.6.

Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A method for processing a substrate is provided. The method includes the following operations: placing a substrate over a first injector in a substrate processing apparatus, the substrate having a front surface and a back surface opposite to the front surface, and the front surface having a plurality of concentric regions; adjusting a temperature of each of the plurality of concentric regions by controlling at least one of a flow rate and a temperature associated with a fluid dispensing from the first injector; and rotating the substrate by a spin base disposed below the substrate, the substrate is rotated with respect to a center axis perpendicular to the front surface thereof when adjusting the temperature. The spin base includes a ring opening for rotating relative to the first injector, and the first injector is displaced from a projection of a center of the substrate from a top view perspective.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.

Abstract: A method for processing a substrate is provided. The method includes the following operations: placing a substrate over a first injector in a substrate processing apparatus, the substrate having a front surface and a back surface opposite to the front surface, and the front surface having a plurality of concentric regions; adjusting a temperature of each of the plurality of concentric regions by controlling at least one of a flow rate and a temperature associated with a fluid dispensing from the first injector; and rotating the substrate by a spin base disposed below the substrate, the substrate is rotated with respect to a center axis perpendicular to the front surface thereof when adjusting the temperature. The spin base includes a ring opening for rotating relative to the first injector, and the first injector is displaced from a projection of a center of the substrate from a top view perspective.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.

Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes a plurality of holding members and at least a first injector. The plurality of holding members are configured to hold a substrate. The substrate includes a front surface and a back surface opposite to the front surface. The first injector is below the holding members and is configured to face the back surface of the substrate. The first injector is displaced from a projection of a center of the substrate from a top view perspective. A method for processing a substrate is also provided.

Abstract: The application discloses a touch controller to determine a position where a user touches a touchscreen. The touchscreen includes a first transmitting electrode, a second transmitting electrode and a receiving electrode. The touch controller includes a signal generation module and a demodulation module. The signal generation module is configured to perform an in-phase code transmission at a first time so that the receiving electrode receives an in-phase code receiving signal correspondingly, and perform an inverting-phase code transmission at a second time so that the receiving electrode receives an inverting-phase code receiving signal correspondingly. The demodulation module is configured to determine the position where the user touches the touchscreen according to the in-phase code receiving signal corresponding to the first time and the inverting-phase code receiving signal corresponding to the second time.

Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Abstract: A method includes forming a gate trench over a semiconductor fin. The gate trench includes an upper portion surrounded by first gate spacers and a lower portion surrounded by second gate spacers and the first gate spacers. The method includes forming a metal gate in the lower portion of the gate trench. The metal gate is disposed over a first portion of a gate dielectric layer. The method includes depositing a metal material in the gate trench to form a gate electrode overlaying the metal gate in the lower portion of the gate trench, while keeping sidewalls of the first gate spacers and upper surfaces of the second gate spacer overlaid by a second portion of the gate dielectric layer. The method includes removing the second portion of the gate dielectric layer, while remaining the gate electrode substantially intact.