Patents by Inventor Po-Zen Chen
Po-Zen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210036179Abstract: A method includes forming image sensors in a semiconductor substrate. A first alignment mark is formed close to a front side of the semiconductor substrate. The method further includes performing a backside polishing process to thin the semiconductor substrate, forming a second alignment mark on the backside of the semiconductor substrate, and forming a feature on the backside of the semiconductor substrate. The feature is formed using the second alignment mark for alignment.Type: ApplicationFiled: May 4, 2020Publication date: February 4, 2021Inventors: Chih Wei Sung, Chung-Bin Tseng, Keng-Ying Liao, Yen-Jou Wu, Po-Zen Chen, Su-Yu Yeh, Ching-Chung Su
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Publication number: 20210020669Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.Type: ApplicationFiled: July 15, 2019Publication date: January 21, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yu LIN, Keng-Ying LIAO, Huai-Jen TUNG, Po-Zen CHEN, Su-Yu YEH, Chia-Yun CHEN, Ta-Cheng WEI
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Patent number: 10879289Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a metal catalyst layer on an etching area of the semiconductor substrate; performing a wet etch process to the semiconductor substrate to etch the etching area of the semiconductor substrate under the metal catalyst layer, thereby forming a trench in the semiconductor substrate; and removing the metal catalyst layer from the semiconductor substrate after performing the wet etch process.Type: GrantFiled: July 15, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Yu Lin, Keng-Ying Liao, Huai-Jen Tung, Po-Zen Chen, Su-Yu Yeh, Chia-Yun Chen, Ta-Cheng Wei
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Publication number: 20200373344Abstract: The present disclosure describes the formation of a pad structure in an image sensor device using a sacrificial isolation region and a silicon oxide based stack with no intervening nitride etch-stop layers. The image sensor device includes a semiconductor layer comprising a first horizontal surface opposite to a second horizontal surface; a metallization layer formed on the second horizontal surface of the semiconductor layer, where the metallization layer includes a dielectric layer. The image sensor device also includes a pad region traversing through the semiconductor layer from the first horizontal surface to the second horizontal surface. The pad region includes an oxide layer with no intervening nitride layers formed on the dielectric layer of the metallization layer and a pad structure in physical contact with a conductive structure of the metallization layer.Type: ApplicationFiled: May 24, 2019Publication date: November 26, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huai-jen TUNG, Ching-Chung SU, Keng-Ying LIAO, Po-Zen CHEN, Su-Yu YEH, S.Y. CHEN
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Patent number: 10811423Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: GrantFiled: November 30, 2018Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Publication number: 20200279887Abstract: In a method for forming a semiconductor device photo-sensing regions are formed over a frontside of a substrate. A first layer is formed over a backside of the substrate and is patterned to form a plurality of grid lines. The grid lines can define a plurality of first areas and a plurality of second areas. A second layer maybe formed over exposed portions of the backside, the gridlines, the first areas, and the second areas and a third layer may be formed over the second layer. The second and third layer may have different etch rates and the third layer is pattern so as to remove the third layer from over the plurality of first areas.Type: ApplicationFiled: February 28, 2019Publication date: September 3, 2020Applicant: Taiwan Semiconductor Manufacturing Co.Inventors: H. L. Chen, Huai-jen Tung, Keng-Ying Liao, Po-Zen Chen, Su-Yu Yeh, Chih Wei Sung
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Patent number: 10665466Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: GrantFiled: December 13, 2018Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Keng-Ying Liao, Chung-Bin Tseng, Po-Zen Chen, Yi-Hung Chen, Yi-Jie Chen
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Patent number: 10658269Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: GrantFiled: April 19, 2019Date of Patent: May 19, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
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Publication number: 20190252295Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: ApplicationFiled: April 19, 2019Publication date: August 15, 2019Inventors: TSUNG-HAN TSAI, VOLUME CHIEN, YUNG-LUNG HSU, CHUNG-BIN TSENG, KENG-YING LIAO, PO-ZEN CHEN
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Patent number: 10269814Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: GrantFiled: April 20, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Patent number: 10269684Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: GrantFiled: November 16, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
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Publication number: 20190115222Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: ApplicationFiled: December 13, 2018Publication date: April 18, 2019Inventors: Keng-Ying LIAO, Chung-Bin TSENG, Po-Zen CHEN, Yi-Hung CHEN, Yi-Jie CHEN
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Publication number: 20190109147Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Keng-Ying LIAO, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Patent number: 10163646Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: GrantFiled: February 27, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Ying Liao, Chung-Bin Tseng, Po-Zen Chen, Yi-Hung Chen, Yi-Jie Chen
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Patent number: 10056316Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: GrantFiled: November 27, 2017Date of Patent: August 21, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
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Patent number: 10008530Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The BSI image sensor includes a semiconductive substrate, a deep trench isolation (DTI) at a back side of the semiconductive substrate, and a dielectric layer. the dielectric layer includes a top portion over the back side, and a side portion lined to a sidewall of the DTI. The BSI image sensor includes a planarization stop layer disposed conformally on top of the dielectric layer. The planarization stop layer includes a top section on the top portion, a side section lined against the side portion, and a first transmittance. The BSI image sensor includes a low-transparent material inside the DTI, and the low-transparent material includes a second transmittance. The second transmittance is lower than the first transmittance.Type: GrantFiled: January 30, 2015Date of Patent: June 26, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Keng-Ying Liao, Chung-Bin Tseng, Cheng-Hsien Chou, Jiech-Fun Lu, Po-Zen Chen, Yi-Hung Chen
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Publication number: 20180082928Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: ApplicationFiled: November 27, 2017Publication date: March 22, 2018Inventors: TSUNG-HAN TSAI, VOLUME CHIEN, YUNG-LUNG HSU, CHUNG-BIN TSENG, KENG-YING LIAO, PO-ZEN CHEN
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Publication number: 20180082927Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: ApplicationFiled: November 16, 2017Publication date: March 22, 2018Inventors: TSUNG-HAN TSAI, VOLUME CHIEN, YUNG-LUNG HSU, CHUNG-BIN TSENG, KENG-YING LIAO, PO-ZEN CHEN
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Patent number: 9831154Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.Type: GrantFiled: July 14, 2014Date of Patent: November 28, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tsung-Han Tsai, Volume Chien, Yung-Lung Hsu, Chung-Bin Tseng, Keng-Ying Liao, Po-Zen Chen
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Publication number: 20170170024Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: ApplicationFiled: February 27, 2017Publication date: June 15, 2017Inventors: Keng-Ying LIAO, Chung-Bin TSENG, Po-Zen CHEN, Yi-Hung CHEN, Yi-Jie CHEN