Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.

Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.

Abstract: The present disclosure provides a method for manufacturing a semiconductor isolation structure, including providing a substrate with a top surface; forming a patterned mask over the top surface; forming a trench through the patterned mask in the substrate by a directional etch comprising nitrogen-containing substance, wherein an aspect ratio of the trench is formed to be greater than about 18, and a ratio of a width of a narrowest portion and a width of a widest portion of the isolation region is formed to be greater than about 0.7; and filling the trench with insulating materials. The present disclosure also provides an image sensing device, including a radiation sensing region with a first isolation region separating adjacent radiation detecting units and a peripheral region, wherein an aspect ratio of the first isolation region is greater than about 18.

Abstract: Some embodiments of the present disclosure provide a back side illuminated (BSI) image sensor. The BSI image sensor includes a semiconductive substrate, a deep trench isolation (DTI) at a back side of the semiconductive substrate, and a dielectric layer. the dielectric layer includes a top portion over the back side, and a side portion lined to a sidewall of the DTI. The BSI image sensor includes a planarization stop layer disposed conformally on top of the dielectric layer. The planarization stop layer includes a top section on the top portion, a side section lined against the side portion, and a first transmittance. The BSI image sensor includes a low-transparent material inside the DTI, and the low-transparent material includes a second transmittance. The second transmittance is lower than the first transmittance.

Abstract: The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 ?m to about 0.2 ?m.

Abstract: The present disclosure provides a method for manufacturing a semiconductor isolation structure, including providing a substrate with a top surface; forming a patterned mask over the top surface; forming a trench through the patterned mask in the substrate by a directional etch comprising nitrogen-containing substance, wherein an aspect ratio of the trench is formed to be greater than about 18, and a ratio of a width of a narrowest portion and a width of a widest portion of the isolation region is formed to be greater than about 0.7; and filling the trench with insulating materials. The present disclosure also provides an image sensing device, including a radiation sensing region with a first isolation region separating adjacent radiation detecting units and a peripheral region, wherein an aspect ratio of the first isolation region is greater than about 18.

Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.

Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.

Abstract: A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.

Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Abstract: A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.

Abstract: A dual damascene process. A first photoresist layer with a first opening corresponding to a trench pattern is formed on a dielectric layer. A second photoresist layer with a second opening corresponding to a via pattern smaller then the trench pattern is formed on the first photoresist layer and extends to a portion of the dielectric layer. The second photoresist layer has a material character different from the first photoresist layer. A via etching process using the second photoresist as a mask is performed to form a via hole passing through the dielectric layer. A photoresist ashing process is performed to remove the second photoresist layer. A trench etching process using the first photoresist layer as a mask is performed to form a trench in the upper portion of the dielectric layer. The via etching process, the photoresist ashing process and the trench etching process are performed as a continuous process in one chamber.

Abstract: A adjustable upper coil or electrode for a reaction chamber apparatus useable in semiconductor processing, is constructed so that its shape may be selectively changed or so at least two portions thereof may be selectively driven at different power and/or frequencies. The adjustable upper coil or electrode, therefore, enables the plasma density distribution in the reaction chamber apparatus to be selectively controlled.

Abstract: A method of controlling gate formation of semiconductor devices includes determining the correlation between the step heights of isolation structures and the over-etching time by measuring step heights of isolation structures, determining an over-etching time based on the step heights, and etching gates using the over-etching time. The method may include an after-etching-inspection to measure the gate profile and fine-tune the gate formation control. Within-wafer uniformity can also be improved by measuring the step height uniformity on a wafer and adjusting gate formation processes.

Abstract: A system for decoding and searching the content of a file and the operation method thereof are disclosed, wherein the present invention is utilized in an automated material handling system (AMHS). By utilizing the present invention, the lot historical record file is downloaded at a predetermined time, and then a decoding device is utilized to decode the content of the lot historical record file and a decoded result is obtained. The decoded result will be stored in an online database, so that the staff can search and check the content of the lot historical record file by connecting to the online database in internet information service through internet or other ways. Therefore, not only the searching speed is rapid, but also the loading of the AMHS is not increased. Meanwhile, wherever the maintainer is, he can maintain the lot historical record file through internet in any time.