Abstract: A display panel and a display device are provided. The display panel includes a display region and a non-display region. The non-display region includes a demultiplexing circuit, a fanout wire, and a clock signal line. An input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line in the display region, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line. The display panel further includes an isolation signal line including an isolation portion, and an orthographic projection of the isolation portion on a plane where a substrate is located is between an orthographic projection of the clock signal line on the plane where the substrate is located and an orthographic projection of the fanout wire on the plane where the substrate is located.

Abstract: A display panel and a display device are provided according to embodiments of the application. In the display panel, a first metal electrode layer further includes multiple second metal electrode lines which are located in the same layer as multiple first metal electrode lines. An end of the second metal electrode line is electrically connected with the drain of a thin film transistor; and the other end of the second metal electrode line is electrically connected with the pixel electrode, so that the pixel electrode is electrically connected with the drain of the corresponding thin film transistor through the second metal electrode line. The area occupied by the electric connection region of the pixel electrode and the drain of the corresponding thin film transistor is reduced and the display area of the display panel is increased, when the size and the thickness of the display panel are not increased.

Abstract: Provided are a display panel and a display device. The display panel includes multiple data lines and multiple scanning lines. The multiple data lines intersect with the multiple scanning lines to define multiple pixel units arranged in an array, and the data lines are insulated from the scanning lines; and pixel electrodes of pixel units that are among the multiple pixel units and in at least portion of the array include multiple first branch electrodes arranged in parallel; along a direction of the multiple scanning lines, each of the multiple first branch electrodes includes multiple first branch electrode segments connected sequentially; and an included angle between two adjacently connected first branch electrode segments of the multiple first branch electrode segments is less than 180°.

Abstract: A display panel and a display device are provided. A first main support column and an auxiliary support column are provided between the first substrate and the second substrate in the frame area, and a length of the first main support column is greater than a length of the auxiliary support column. The second substrate includes the base, and further includes the first surface and the second surface located on a side of the second substrate facing the first substrate in the frame area. A height from the second surface to the base is greater than a height from the first surface to the base. An orthographic projection of the first main support column on the base is located within an orthographic projection of the first surface on the base.

Abstract: A shift register includes n shift register units which are cascaded. Each shift register unit includes a shift module and multiple enable modules. The shift module of an i-th-level shift register unit is configured to receive and latch a shift signal output by the shift module in an (i?1)-th-level shift register unit. The multiple enable modules of the i-th-level shift register unit are electrically connected to the shift module of the i-th-level shift register unit, and each of the multiple enable modules is configured to generate a gate driving signal according to the shift signal. n and i are positive integers, 1?i?n.

Abstract: Display panel and display device are provided. Display panel has display area and bezel area and includes first and second panel edges connected and adjacent to each other and extending linearly in different directions, first functional circuit located in the bezel area and including first functional circuit units. First functional circuit units include first, second, and third circuit units. First circuit units are located at side of first panel edge and arranged linearly along first panel edge, second circuit units are located at side of second panel edge and arranged linearly along second panel edge, third circuit unit is located between first and second circuit units and close to position where first panel edge is connected to second panel edge. One third circuit unit is arranged in direction inclined to a direction in which one first circuit unit is arranged and direction in which one second circuit unit is arranged.

Abstract: A display panel includes data lines and scanning lines in a display region, and a demultiplexer in a non-display region. The demultiplexer includes m branches. m is an integer. m?2. Each branch includes a switching transistor which includes a first electrode coupled with an input terminal of the demultiplexer, a second electrode coupled with one of the data lines, and a control electrode for receiving a switching control signal. The demultiplexer includes a first demultiplexer including a compensation transistor, of which first and second electrodes are short-circuited. The compensation transistor is coupled with the data line and has a control electrode for receiving a compensation control signal. The compensation control signal received by the compensation transistor in the branch has one functional rising edge in a period during which the scanning line provides an effective level signal once.

Abstract: Provided are a display panel and a display device. The display panel includes multiple data lines and multiple scanning lines. The multiple data lines intersect with the multiple scanning lines to define multiple pixel units arranged in an array, and the data lines are insulated from the scanning lines; and pixel electrodes of pixel units that are among the multiple pixel units and in at least portion of the array include multiple first branch electrodes arranged in parallel; along a direction of the multiple scanning lines, each of the multiple first branch electrodes includes multiple first branch electrode segments connected sequentially; and an included angle between two adjacently connected first branch electrode segments of the multiple first branch electrode segments is less than 180°.

Abstract: A shift register includes n shift register units which are cascaded. Each shift register unit includes a shift module and multiple enable modules. The shift module of an i-th-level shift register unit is configured to receive and latch a shift signal output by the shift module in an (i?1)-th-level shift register unit. The multiple enable modules of the i-th-level shift register unit are electrically connected to the shift module of the i-th-level shift register unit, and each of the multiple enable modules is configured to generate a gate driving signal according to the shift signal. n and i are positive integers, 1?i?n.

Abstract: A display panel and a display device are provided according to embodiments of the application. In the display panel, a first metal electrode layer further includes multiple second metal electrode lines which are located in the same layer as multiple first metal electrode lines. An end of the second metal electrode line is electrically connected with the drain of a thin film transistor; and the other end of the second metal electrode line is electrically connected with the pixel electrode, so that the pixel electrode is electrically connected with the drain of the corresponding thin film transistor through the second metal electrode line. The area occupied by the electric connection region of the pixel electrode and the drain of the corresponding thin film transistor is reduced and the display area of the display panel is increased, when the size and the thickness of the display panel are not increased.

Abstract: A display panel and a display device are provided. The display panel includes: a display region and a non-display region surrounding the display region; multiple gate lines; and multiple data lines. The gate lines include regular gate lines and irregular gate lines. In the display region, the regular gate lines and the irregular gate lines are extended in a first direction, and a length of a part of the regular gate line in the display region is greater than a length of a part of the irregular gate line in the display region. The data lines include regular data lines and irregular data lines, and an extension direction of the regular data lines and the irregular data lines intersects with the first direction.

Abstract: Provided are a display panel, a display device, and a mask. The display panel includes an array substrate. The array substrate includes a base substrate and first wires and second wires located on one side of the base substrate. The orthographic projections of the first wires on a plane where the base substrate is located intersect the orthographic projections of the second wires on the plane where the base substrate is located; and wire widths of the first wires at intersections are smaller than at least part of wire widths of the first wires at positions other than the intersections, and/or wire widths of the second wires at intersections are greater than at least part of wire widths of the second wires at positions other than the intersections.

Abstract: A display panel and a display device are provided. A first main support column and an auxiliary support column are provided between the first substrate and the second substrate in the frame area, and a length of the first main support column is greater than a length of the auxiliary support column. The second substrate includes the base, and further includes the first surface and the second surface located on a side of the second substrate facing the first substrate in the frame area. A height from the second surface to the base is greater than a height from the first surface to the base. An orthographic projection of the first main support column on the base is located within an orthographic projection of the first surface on the base.

Abstract: Provided are an array substrate and display device. The array substrate includes a base substrate; a fingerprint recognition unit with a light sensing structure; a light blocking layer and an electrode connecting structure arranged at a side of the light sensing structure facing away from the base substrate. The light blocking layer is provided with a collimation hole. A vertical projection of the collimation hole on the base substrate is partially overlapped with a vertical projection of the light sensing structure on the base substrate. An insulation layer is arranged between the electrode connecting structure and the light sensing structure. The insulation layer is provided with an electrode via. The electrode connecting structure is connected to the light sensing structure through the electrode via. The vertical projection of the collimation hole on the base substrate is not overlapped with a vertical projection of the electrode via on the base substrate.

Abstract: An irregular display panel and a display device are provided. A display region has an irregular boundary. The display panel includes low-luminance pixels, and normal pixels arranged away from the irregular boundary. The pixel rows and/or the pixel columns include pixel groups each including a first pixel group and a second pixel group. The number of pixels adjacent to the irregular boundary in the first pixel group is greater than that in the second pixel group, and the number of low-luminance pixels of the first pixel group is greater than or equal to that of the second pixel group. The pixel includes at least three sub pixels each including an electrode having at least one slit. The total slit lengths of the low-luminance pixels in a same pixel group increase gradually in a direction from the irregular boundary to the display region.

Abstract: A display panel and a display device are provided. The display panel includes: a display region and a non-display region surrounding the display region; multiple gate lines; and multiple data lines. The gate lines include regular gate lines and irregular gate lines. In the display region, the regular gate lines and the irregular gate lines are extended in a first direction, and a length of a part of the regular gate line in the display region is greater than a length of a part of the irregular gate line in the display region. The data lines include regular data lines and irregular data lines, and an extension direction of the regular data lines and the irregular data lines intersects with the first direction.

Abstract: An array substrate includes: a display region, a non-display region surrounding the display region, at least one notch in the non-display region, and multiple gate lines. The gate lines include regular gate lines and irregular gate lines. The regular gate line is located in the display region and extends in a first direction. The irregular gate line includes a regular section located in the display region and extends in the first direction and an irregular section located in the non-display region around the notch. The regular section and the irregular section of the same irregular gate line are electrically connected. The irregular section includes a first sub-section and/or a second sub-section. The first sub-section and the second sub-section of the same irregular section are electrically connected to each other. A resistivity of the first sub-section is greater than a resistivity of the second sub-section.

Abstract: A display panel and a display device are provided. The display panel includes: a display region and a non-display region surrounding the display region; multiple gate lines; and multiple data lines. The gate lines include regular gate lines and irregular gate lines. In the display region, the regular gate lines and the irregular gate lines are extended in a first direction, and a length of a part of the regular gate line in the display region is greater than a length of a part of the irregular gate line in the display region. The data lines include regular data lines and irregular data lines, and an extension direction of the regular data lines and the irregular data lines intersects with the first direction.

Abstract: A display panel and a display device are provided. The display panel includes multiple pixel units. In each of the pixel units, the area of an opening region of at least one sub-pixel is different from the area of an opening region of other sub-pixels. There is an adjustment capacitance between the drain of the thin film transistor and/or the first electrode in each sub-pixel and the scan line corresponding to the sub-pixel, and the sub-pixel having a smaller area of the opening region corresponds to a smaller value of the adjustment capacitance. By adjusting the value of the adjustment capacitance corresponding to the sub-pixels with different areas of opening regions, the optimal Vcom of all the sub-pixels is the same, so that all the sub-pixels operate under the same optimal Vcom.

Abstract: Provided are a mobile terminal and a method for receiving and sending a light fidelity (LIFI) signal of the mobile terminal. The mobile terminal includes a display device. The display device includes a plurality of light emitting elements and a LIFI signal sending control assembly. The LIFI signal sending control assembly is electrically connected to at least one of the plurality of light emitting elements. The display device is configured to control, according to a display signal, the plurality of light emitting elements to emit light for displaying a to-be-displayed picture, and the display device is further configured to control, according to a LIFI sending signal of the LIFI signal sending control assembly, the at least one of the plurality of light emitting elements electrically connected to the LIFI signal sending control assembly to emit a first LIFI signal.