DISPLAY PANEL AND DISPLAY DEVICE
A display panel and a display device are provided. The display panel includes a display region and a non-display region. The non-display region includes a demultiplexing circuit, a fanout wire, and a clock signal line. An input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line in the display region, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line. The display panel further includes an isolation signal line including an isolation portion, and an orthographic projection of the isolation portion on a plane where a substrate is located is between an orthographic projection of the clock signal line on the plane where the substrate is located and an orthographic projection of the fanout wire on the plane where the substrate is located.
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This application claims priority to Chinese patent application No. 202311132888.X filed with the China National Intellectual Property Administration (CNIPA) on Sep. 4, 2023, the disclosure of which is incorporated herein by reference in its entirety.
TECHNICAL FIELDThe present disclosure relates to the field of display techniques and, in particular, to a display panel and a display device.
BACKGROUNDWith the development of display technology, display panels have been widely used in people's production and life. However, there are still some technical issues to be addressed in the display panels in the related art, for example, interference of signal transmission between different signal lines in the existing display panels and the like.
SUMMARYA display panel and a display device are provided according to embodiments of the present disclosure, which can avoid the signal coupling between different wires by providing an isolation signal line, thereby ensuring the stability of signal transmission of the display panel.
A display panel is provided according to an embodiment of the present disclosure, and the display panel includes a substrate, a display region and a non-display region.
The display region includes multiple data lines, and the non-display region includes a demultiplexing circuit, a fanout wire, and a clock signal line. An input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line of the data lines, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line.
The display panel further includes an isolation signal line, the isolation signal line includes an isolation portion, and an orthographic projection of the isolation portion on a plane where the substrate is located is between an orthographic projection of the clock signal line on the plane where the substrate is located and an orthographic projection of the fanout wire on the plane where the substrate is located.
A display device is provided according to an embodiment of the present disclosure, and the display device includes the display panel according to any feature of the first aspect.
To illustrate technical schemes in embodiments of the present disclosure more clearly, drawings used in description of the embodiments are briefly described hereinafter. Apparently, the drawings described hereinafter merely illustrate some embodiments of the present disclosure, and for the person of ordinary skill in the art, other drawings can be obtained based on these drawings without making creative efforts.
For enabling the person skilled in the art to better understand the schemes of the present disclosure, the technical schemes in embodiments of the present disclosure are described clearly and completely in conjunction with the drawings in embodiments of the present disclosure. Apparently, the embodiments described below are part, rather than all, of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by the person skilled in the art on the premise that no creative efforts are made are within the scope of the present disclosure.
It is to be noted that the terms “first”, “second” and the like in the description, claims and the above drawings of the present disclosure are intended to distinguish between similar objects and are not necessarily used to describe a particular order or sequence. It is to be appreciated that the data used in this way is interchangeable where appropriate so that the embodiments of the present disclosure described herein may also be implemented in a sequence besides those sequences illustrated or described herein. Furthermore, terms such as “include”, “have”; and any deformation thereof, are intended to cover non-exclusive inclusion, e.g., a system, product, or apparatus including a series of units is not necessarily limited to those steps or units expressly listed, but may include other units not expressly listed or inherent to such system, product or apparatus.
Referring to
For example, the sub-pixels in the display region 100 may be organic light-emitting diodes (OLED), mini light-emitting diodes (LEDs), micro LEDs, quantum dot light-emitting diodes (QLED) or liquid crystal sub-pixels, etc., which are not limited in the similar embodiments of the present disclosure. The sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. The arrangement of sub-pixels of different colors may be a diamond pixel arrangement, and may also be a standard red/green/blue (RGB) arrangement, a delta pixel arrangement, a pearl pixel arrangement, a 2in1 pixel arrangement, or the like. The arrangement of the sub-pixels is not limited by the embodiments of the present disclosure.
For example, the pixel circuit for electrically connecting the sub-pixels may be a “2T1C” circuit, a “7T1C” circuit, a “7T2C” circuit, or the like. The “2T1C circuit” refers to that the pixel circuit includes two thin-film transistors (T) and one capacitor (C), and the “7T1C” circuit and “7T2C” circuit may be deduced by analogy. The number of thin-film transistors and capacitors in the pixel circuit may be set by the person skilled in the art according to practical requirements, which is not further described and limited by the embodiments of the present disclosure.
The non-display region 200 at least partially surrounds the display region 100, and the non-display region 200 may be a lower bezel region of the display panel 10. The non-display region 200 includes a demultiplexing circuit 210, a fanout wire 230 and a clock signal line 240. The demultiplexing circuit 210 is electrically connected to the fanout wire 230, the clock signal line 240 and the data lines 110, respectively, so as to realize that one fanout wire 230 may be electrically connected to multiple data lines 110, thereby facilitating the realization of a narrow bezel design of the display panel 10 while ensuring the display effect of the display panel 10. The demultiplexing circuit 210 is a combinational logic circuit that may assign an input signal transmitted by one input line to any one of multiple individual output lines at a time. Referring to
Further, the fanout wire 230 and the clock signal line 240 transmit different signals respectively, for example, the fanout wire 230 transmits a data signal for display, and the clock signal line 240 transmits a clock control signal for controlling the switch units 211 to be turned on or off. When the two types of wires are relatively close to each other, signal coupling is caused between the fanout wire 230 and the clock signal line 240, and interference is generated between the clock signal line 240 and the fanout wire 230. In particular, the signal in the fanout wire 230 causes relatively large interference on the clock signal of the clock signal line 240, which adversely affects the accuracy and stability of the signal transmission of both the fanout wire 230 and the clock signal line 240. Based on this, the display panel 10 according to an embodiment of the present disclosure further includes an isolation signal line 300, and the isolation signal line 300 includes an isolation portion 310 located between the clock signal line 240 and the fanout wire 230 in the direction of the projection on the substrate 400. With reference to
It is to be noted that
In summary, in the display panel according to the embodiment of the present disclosure, the orthographic projection of the isolation portion on the plane where the substrate is located is between the orthographic projection of the clock signal line on the plane where the substrate is located and the orthographic projection of the fanout wire on the plane where the substrate is located, the isolation portion can block interference between the signals of the clock signal line and the fanout wire, reduce the coupling between the clock signal line and the fanout wire, ensure the stability of overall signal transmission of the display panel, and further ensure display effect of the display panel.
With continued reference to
Referring to
Further, with continued reference to
Further, as shown in
Referring to
Further, referring to
Referring to
With the adjustment for the arrangement position of the film layer of the isolation portion 310, the interference between the clock signal line 240 and the fanout wire 230 can be effectively avoided, the signal transmission accuracy can be improved, and the display effect can be improved. In an embodiment,
In an embodiment, the projection of the isolation portion 310 on the substrate 400 is located between the projection of the clock signal line 240 on the substrate 400 and the projection of the fanout wire 230 on the substrate 400. Moreover, in the thickness direction of the display panel 10, the film layer in which the isolation portion 310 is arranged is not out of the range defined by the film layer in which the fanout wire 230 is located and the film layer in which the clock signal line 240 is located, thereby effectively ensuring that the isolation portion 310 plays a role of isolating the signal interference between the clock signal line 240 and the fanout wire 230 in different dimensions.
For example, referring to
Illustratively, referring to
In an embodiment,
Referring to
On the basis of the embodiments described above, the film layer in which the isolation signal line is located is not limited by the embodiments of the present application. For example, the display panel may include a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer and a sixth metal layer. The first metal layer may include a gate of a low-temperature polysilicon thin-film transistor, the second metal layer may include one of the capacitor substrates of a storage capacitor, the third metal layer may include a gate of an oxide thin-film transistor, the fourth metal layer may include a jumper structure between other metal layers, the fifth metal layer may include a source and a drain of the thin-film transistor, and the sixth metal layer may include connection wires in the structure of fanout wires arranged in the display region. The fanout in AA (FIAA) structure may be understood as that a fanout wire located in the non-display region (e.g., a fanout wire region) is electrically connected to a data signal line in the display region by a connecting wire in the display region, in this way, the number of wires arranged in the fanout wire region can be reduced and the space occupied by the non-display region of the display panel 10 can be reduced. When the fanout wire, the isolation signal line and the clock signal line are arranged in the same layer, the three may be located in any one of the first metal layer to the sixth metal layer mentioned above, for example, the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, or the like. When the isolation signal line is arranged in the same layer as the fanout wire but in a different layer from the clock signal line, the isolation signal line may be located in any one of the first metal layer to the sixth metal layer, and the clock signal line is located in any one of the layers different from the layer of the isolation signal line. For example, the isolation signal line and the fanout wire are located in the first metal layer, and the clock signal line is located in the second metal layer, the third metal layer, the fourth metal layer, or the like. When the isolation signal line is arranged in the same layer as the clock signal line but in a different layer from the fanout wire, the isolation signal line may be located in any one of the first metal layer to the sixth metal layer mentioned above, and the fanout wire is located in any one of the layers different from the layer of the isolation signal line. For example, the isolation signal line and the clock signal line are located in the first metal layer, and the fanout wire is located in the second metal layer, the third metal layer, the fourth metal layer, or the like. When the isolation signal line is located between the film layer where the fanout wire is located and the film layer where the clock signal line is located, the fanout wire, the isolation signal line, and the clock signal line are all arranged in different layers, and it is required to ensure that the isolation signal line is located between the film layer where the fanout wire is located and the film layer where the clock signal line is located. For example, the fanout wire is located in the first metal layer, the isolation signal line is located in the second metal layer, the clock signal line is located in the third metal layer, and for another example, the clock signal line is located in the first metal layer, the isolation signal line is located in the third metal layer, and the fanout wire is located in the fourth metal layer. The film layers where the fanout wire, the isolation signal line, and the clock signal line are located are not limited by the embodiments of the present disclosure, the fanout wire, the isolation signal line, and the clock signal line may be located in the metal layers in an existing display panel, thus ensuring that the film layer arrangement of the fanout wire, the isolation signal line and the clock signal line is simple, and also facilitating the simplicity of the film layer arrangement of the entire display panel.
Referring to
In an embodiment, with continued reference to
Referring to
Further, the isolation signal line 300 for isolating the fanout wire 230 from the clock signal line 240 may be more than just a fixed potential signal line, for example, the isolation signal line 300 may include both the display test signal line and the common voltage signal line, the quantity and type of the isolation signal line are not limited by the embodiments of the present disclosure. Meanwhile, in this manner, it can further reflect the flexibility of the arrangement of the isolation signal line 300.
In an embodiment,
Before the driver chip 220 is bound to the display panel 10, a visual test, that is, a VT test, is generally performed to verify the display effect of the display panel 10, and the display test signal line 300vt is used for receiving a signal output by the display test signal terminal vt is received by the display test signal line 300vt, so that the screen of the display panel 10 may display a pure color image or a checkerboard image, thereby implementing the test of the display panel 10.
Further, referring to
In an embodiment, the display test signal line 300vt includes the isolation portion 310 and the first connection portion 320. The orthographic projection of the isolation portion 310 on the plane where the substrate 400 is located is between the orthographic projection of the clock signal line 240 on the plane where the substrate 400 is located and the orthographic projection of the fanout wire 230 on the plane where the substrate 400 is located, for reducing the signal interference between the clock signal line 240 and the fanout wire 230. The first connection portion 320 is configured to electrically connect the display test signal terminal vt to the isolation portion 310, thus, it can be ensured through the first connection portion 320 that the fixed potential signal is connected to the isolation portion 310, and the shielding on signals is implemented, thereby further ensuring the display stability of the display panel 10. It is to be noted that, as shown in
Further, the display panel 10 also includes an input bonding terminal 222 and an output bonding terminal 221, and the input bonding terminal 222 and the output bonding terminal 221 are configured to be electrically connected to the driver chip 220 in a bonding manner. The related signals enter the driver chip 220 through the input bonding terminal 222 and are subjected to related calculations, and the signals after the calculation process are transmitted to the fanout wire 230 through the output bonding terminal 221. A certain distance exists between the input bonding terminal 222 and the output bonding terminal 221, and a portion of the first connection portion 320 in the display test signal line 300vt is disposed between the input bonding terminal 222 and the output bonding terminal 221, so that an additional wiring space cannot be provided for the display test signal line 300vt, facilitating implementation of a narrow bezel design of the display panel 10. For example, referring to
In an embodiment, referring to
In an embodiment, the display test signal line 300vt includes the display test switch signal line 300vt1 and the display test data signal line 300vt2. The display test switch signal line 300vt1 is configured to control the on/off state of a switch unit in the display test structure, and the display test data signal line 300vt2 is configured to transmit a display test signal to the data line 110 through the switch unit in the display test structure.
In an embodiment, the VT test is to provide a potential signal for the display test purpose to the display test switch signal line and the display test data signal line through test equipment, and after the VT test finishes, a fixed potential signal is provided for at least part of signal lines in the display test switch signal lines 300vt1 and the display test data signal lines 300vt2 by a driver chip 220 or a flexible circuit board, so that the display test signal line also serves as the isolation wire between the clock signal line and the fanout wire, thus the issue of signal coupling between the clock signal line and the fanout wire can be reduced, the stability of the signals transmitted in the fanout wire and the clock signal line can be ensured, and the display effect of the display panel can be improved.
Referring to
Referring to
For example, referring to
It is to be noted that when the isolation signal line includes the display test signal line and the common voltage signal line, and the common voltage signal line includes the first common voltage signal line 300c1 and the second common voltage signal line 300c2, the first common voltage signal line 300c1 includes the first isolation portion 300c11 located between the display test signal line 300vt and the fanout wire 230, and the second common voltage signal line 300c2 includes the second isolation portion 300c21 located between the display test signal line 300vt and the clock signal line 240. In this case, the display test signal line 300vt may or may not receive a fixed potential signal. In an embodiment, when the display test signal line 300vt receives a fixed potential signal, the first common voltage signal line 300c1, the display test signal line 300vt and the second common voltage signal line 300c2 all can further shield the coupling interference between the clock signal line 240 and the fanout wire 230, thereby further improving the stability of the display signal and the clock signal. Alternatively, when the display test signal line does not receive a fixed potential signal, the fixed potential signals provided through the first common voltage signal line 300c1 and the second common voltage signal line 300c2 can ensure a good isolation effect between the clock signal line 240 and the fanout wire 230, and in this case, it is not necessary to provide an independent fixed potential signal for the display test signal line, that is, the driver chip or the flexible circuit board does not need to provide an independent fixed potential signal for the display test terminal, thus the simple control logic of the driver chip and the flexible circuit board can be ensured, and the working efficiency of the display panel or the flexible circuit board is relatively efficient.
In an embodiment, referring to
Further, the orthographic projection of the fourth isolation portion 310a on the plane in which the substrate 400 is located overlaps the orthographic projection of the fifth isolation portion 310b on the plane in which the substrate 400 is located, the fourth isolation portion 310a and the fifth isolation portion 310b are arranged in different layers, so that the space occupied by the entire isolation signal line can be reduced, thereby facilitating the narrow bezel design of the display panel 10. Illustratively, as for the positions of the fourth isolation portion 310a and the fifth isolation portion 310b, reference may be made to
It is to be noted that, in
In an embodiment, referring to
Further, referring to
In an embodiment, referring to
Further, referring to
In an embodiment,
Still referring to
In an embodiment, the display panel 10 further includes multiple display voltage signal lines, for example, a positive power signal line PVDD or a negative power signal line PVEE, the categories of the display voltage signal lines are not limited by the embodiments of the present disclosure. Further, the common voltage signal line 300c used as the isolation signal line 300 is provided independently, that is, the common voltage signal line 300c is arranged to be insulated from the display voltage signal lines, in other words, the common voltage signal line does not need to be reused as the display voltage signal line, so that a high setting freedom degree of the common voltage signal line 300c can be ensured, and additional considerations of adjustment on the wiring of the display voltage signal lines or adjustment on the matching degree of the display voltage signal lines for the voltage signals are not required. The common voltage signal line 300c simply requires a single fixed potential terminal leading out from the flexible circuit board. The process has a low cost and a good signal isolation effect, and can further well ensure the display effect of the display panel 10.
As shown in
Referring to
Referring to the demultiplexing circuit shown in
Further, referring to
For example, referring to
For example, referring to
For example, referring to
Further, for the adjustment of the impedances of the clock signal lines 240 with different extension lengths, the adjustment to the width of the wire, the adjustment to the width of the wire at the corner, the adjustment to the notched area of the wire, and the adjustment to the notched area at the corner described above may be partially or all combined, which is not limited by the embodiments of the present disclosure. In other words, no matter whether the widths of the wires are different, the widths of the wires at the corners are gradually changed, or notches are formed in the wires, the essence is to adjust the impedances at different degrees by adjusting the widths of the wires, to ensure that the impedances of the clock signal lines 240 of different lengths are relatively balanced.
Based on the same inventive concept, a display device is further provided according to an embodiment of the present disclosure.
The display device 1 according to an embodiment of the present disclosure may be a mobile phone shown in
It is to be noted that the preceding are only alternative embodiments of the present disclosure and technical principles used therein. It will be understood by the person skilled in the art that the present disclosure is not limited to the specific embodiments described herein. The person skilled in the art can make various apparent changes, readjustments and substitutions without departing from the scope of the present disclosure. Therefore, while the present disclosure has been described in detail through the above-described embodiments, the present disclosure is not limited to the above-described embodiments and may include more other equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
Claims
1. A display panel, comprising a substrate, a display region and a non-display region, wherein
- the display region comprises a plurality of data lines, and the non-display region comprises a demultiplexing circuit, a fanout wire, and a clock signal line; an input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line of the data lines, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line; and
- the display panel further comprises an isolation signal line, the isolation signal line comprises an isolation portion, and an orthographic projection of the isolation portion on a plane in which the substrate is located is between an orthographic projection of the clock signal line on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located.
2. The display panel according to claim 1, wherein the display panel comprises a first fanout wire group and a second fanout wire group, and the first fanout wire group and the second fanout wire group each comprise a plurality of fanout wires;
- the display panel further comprises a first output terminal group and a second output terminal group, each of the first output terminal group and the second output terminal group comprises a plurality of output bonding terminals, the plurality of fanout wires in the first fanout wire group are electrically connected to the plurality of output bonding terminals in the first output terminal group, and the plurality of fanout wires in the second fanout wire group are electrically connected to the output bonding terminals in the second output terminal group; and
- the first output terminal group and the second output terminal group are arranged in a first direction, wherein the first direction is parallel to the plane in which the substrate is located; and in the first direction, at least a portion of the clock signal line is located between the first output terminal group and the second output terminal group.
3. The display panel according to claim 2, wherein the display panel comprises a first driver chip and a second driver chip, wherein the first driver chip is bound and electrically connected to the first output terminal group, and the second driver chip is bound and electrically connected to the second output terminal group.
4. The display panel according to claim 1, wherein a film layer in which the isolation portion is located is not out of a film layer range defined by a film layer in which the fanout wire is located and a film layer in which the clock signal line is located.
5. The display panel according to claim 4, wherein the isolation portion is arranged in a same layer as at least one of the fanout wire and the clock signal line.
6. The display panel according to claim 4, wherein the fanout wire and the clock signal line are arranged in different layers, and the film layer in which the isolation portion is located is between the film layer in which the fanout wire is located and the film layer in which the clock signal line is located.
7. The display panel according to claim 1, wherein the isolation signal line comprises a fixed potential signal line.
8. The display panel according to claim 7, wherein the isolation signal line comprises at least one of a display test signal line, a common voltage signal line, and an electrostatic lead-out wire.
9. The display panel according to claim 8, wherein the isolation signal line comprises the display test signal line;
- the display panel comprises a display test signal terminal;
- the display test signal line comprises the isolation portion and a first connection portion, and the first connection portion is electrically connected to the display test signal terminal and the isolation portion, respectively;
- the display panel further comprises an input bonding terminal and an output bonding terminal, and both the input bonding terminal and the output bonding terminal are connected to a driver chip in a bonding manner; and
- an orthographic projection of a portion of the first connection portion on the plane in which the substrate is located is between an orthographic projection of the input bonding terminal on the plane in which the substrate is located and an orthographic projection of the output bonding terminal on the plane in which the substrate is located.
10. The display panel according to claim 8, wherein the display test signal line comprises at least one of a display test switch signal line and a display test data signal line.
11. The display panel according to claim 8, wherein the isolation signal line comprises the display test signal line and the common voltage signal line;
- the common voltage signal line comprises a first common voltage signal line and a second common voltage signal line; the first common voltage signal line comprises a first isolation portion, the second common voltage signal line comprises a second isolation portion, and the display test signal line comprises a third isolation portion; and
- an orthographic projection of the first isolation portion on the plane in which the substrate is located is between an orthographic projection of the third isolation portion on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located, and an orthographic projection of the second isolation portion on a plane in which the substrate is located is between the orthographic projection of the third isolation portion on the plane in which the substrate is located and an orthographic projection of the clock signal line on the plane in which the substrate is located.
12. The display panel according to claim 8, wherein the isolation signal line comprises the display test signal line and the common voltage signal line;
- the isolation portion comprises a fourth isolation portion and a fifth isolation portion which are arranged in different layers, the display test signal line comprises the fourth isolation portion, and the common voltage signal line comprises the fifth isolation portion; and
- an orthographic projection of the fourth isolation portion on the plane in which the substrate is located overlaps an orthographic projection of the fifth isolation portion on the plane in which the substrate is located.
13. The display panel according to claim 2, wherein the isolation signal line comprises a common voltage signal line;
- the common voltage signal line comprises the isolation portion, and the isolation portion comprises a first isolation sub-segment and a second isolation sub-segment, the first isolation sub-segment is located between the first fanout wire group and the clock signal line, and the second isolation sub-segment is located between the second fanout wire group and the clock signal line;
- the common voltage signal line further comprises a second connection portion and a third connection portion;
- the display panel further comprises a first common voltage signal terminal and a second common voltage signal terminal;
- the second connection portion is electrically connected to the first common voltage signal terminal and the first isolation sub-segment, respectively; and the third connection portion is electrically connected to the second common voltage signal terminal and the second isolation sub-segment, respectively; and
- the isolation portion, the second connection portion and the third connection portion form at least a semi-enclosed structure, the plurality of fanout wires in the first fanout wire group and the second fanout wire group are located outside the semi-enclosed structure, and at least a portion of the clock signal line is located inside the semi-enclosed structure.
14. The display panel according to claim 13, wherein the common voltage signal line further comprises a fourth connection portion, the fourth connection portion is electrically connected to the second connection portion and the third connection portion, respectively, and the fourth connection portion is located on a side of the isolation portion facing away from the display region; and
- the isolation portion, the second connection portion, the third connection portion and the fourth connection portion form a fully-enclosed structure, and the plurality of fanout wires in the first fanout wire group and the second fanout wire group are located outside the fully-enclosed structure, and at least a portion of the clock signal line is located inside the fully-enclosed structure.
15. The display panel according to claim 13, wherein the display panel further comprises a plurality of display voltage signal lines, and the common voltage signal line is arranged to be insulated from the plurality of display voltage signal lines.
16. The display panel according to claim 1, wherein the display panel further comprises a clock signal terminal and a clock signal jumper line, wherein the clock signal line is connected to the clock signal terminal at a first node and is connected to the clock signal jumper line at a second node, and the clock signal jumper line is electrically connected to the demultiplexing circuit; and
- at least a portion of the clock signal line is located on a side of a virtual line facing away from the fanout wire, wherein the virtual line is a straight-line segment connecting the first node to the second node.
17. The display panel according to claim 1, wherein the display panel comprises a plurality of clock signal lines, and two clock signal lines in the plurality of clock signal lines have different extension lengths; and
- the two clock signal lines have signal line sub-segments with different widths.
18. A display device, comprising a display panel, wherein the display panel comprises a substrate, a display region, and a non-display region, wherein the display region comprises a plurality of data lines, and the non-display region comprises a demultiplexing circuit, a fanout wire, and a clock signal line; an input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line of the data lines, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line; and
- the display panel further comprises an isolation signal line, the isolation signal line comprises an isolation portion, and an orthographic projection of the isolation portion on a plane in which the substrate is located is between an orthographic projection of the clock signal line on the plane in which the substrate is located and an orthographic projection of the fanout wire on the plane in which the substrate is located.
19. The display device according to claim 18, wherein the display panel comprises a first fanout wire group and a second fanout wire group, and the first fanout wire group and the second fanout wire group each comprise a plurality of fanout wires;
- the display panel further comprises a first output terminal group and a second output terminal group, each of the first output terminal group and the second output terminal group comprises a plurality of output bonding terminals, the plurality of fanout wires in the first fanout wire group are electrically connected to the plurality of output bonding terminals in the first output terminal group, and the plurality of fanout wires in the second fanout wire group are electrically connected to the output bonding terminals in the second output terminal group; and
- the first output terminal group and the second output terminal group are arranged in a first direction, wherein the first direction is parallel to the plane in which the substrate is located; and in the first direction, at least a portion of the clock signal line is located between the first output terminal group and the second output terminal group.
20. The display device according to claim 19, wherein the display panel further comprises a first driver chip and a second driver chip, wherein the first driver chip is bound and electrically connected to the first output terminal group, and the second driver chip is bound and electrically connected to the second output terminal group.
Type: Application
Filed: Jan 4, 2024
Publication Date: Apr 25, 2024
Applicant: Xiamen Tianma Microelectronics Co., Ltd. (Xiamen)
Inventors: Guangdeng YANG (Xiamen), Yiqiang LIN (Xiamen), Dongxu QIU (Xiamen), Hao WU (Xiamen), Poping SHEN (Xiamen)
Application Number: 18/403,805