Abstract: A semiconductor structure and its fabrication method are provided. The semiconductor structure includes: a substrate, composite layers, a gate structure crossing the composite layers; inner spacers, source/drain layers, and insulating layers. Each composite layer includes channel layers, first openings between the channel layers and the substrate, and second openings between adjacent channel layers. The gate structure is located on sidewalls and top surfaces of the composite layers, and is also located in the second openings and surrounds the channel layers. The inner spacers are located between adjacent channel layers, and between the channel layers and the substrates. The source/drain layers are located in the composite layers on two sides of the gate structure. Sidewalls of the source/drain layers are coplanar with the sidewalls of adjacent inner spacers and end faces of adjacent channel layers. The insulating layers are located in the first openings.

Abstract: Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: Semiconductor devices is provided. The semiconductor device includes a semiconductor substrate having a first region and an adjacent second region; a plurality of adjacent first fins in the first region of the semiconductor substrate; a plurality of adjacent second fins in the second region of the semiconductor substrate; a first type of fin sidewall spacers; a second type of fin sidewall spacers; first doped layers formed between adjacent first type of fin sidewall spacers in the first region; and second doped layers formed between adjacent first type of fin sidewall spacers in the second region.

Abstract: Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming at least one gate structure having a gate dielectric layer on a surface of the semiconductor substrate; forming first sidewall spacers on a first sidewall surface region of the gate structure and covering sidewall surfaces of the gate dielectric layer; forming second sidewall spacers on a second sidewall surface region of the gate structure and top surfaces of the first sidewall spacers and made of a material different from a material of the first sidewall spacers; forming conductive plugs in the dielectric layer at both sides of the gate structure, the first sidewall spacers and the second sidewall spacers; and removing the second sidewall spacers to form air gap spacers above the first sidewall spacers and between the second sidewall surface region of the gate structure and the conductive plugs.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.

Abstract: Semiconductor devices is provided. The semiconductor device includes a semiconductor substrate having a first region and an adjacent second region; a plurality of adjacent first fins in the first region of the semiconductor substrate; a plurality of adjacent second fins in the second region of the semiconductor substrate; a first type of fin sidewall spacers; a second type of fin sidewall spacers; first doped layers formed between adjacent first type of fin sidewall spacers in the first region; and second doped layers formed between adjacent first type of fin sidewall spacers in the second region.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.

Abstract: Tunnel field-effect transistors are provided. A tunnel field-effect transistor (TFET) includes a semiconductor substrate; a gate structure having a first side and an opposing second side formed on the semiconductor substrate. A first doped source/drain layer is formed in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and a channel region of the semiconductor substrate has a plurality of protruding structures protruding toward the channel region under the gate structure. A second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductive type opposite to the first source/drain doping layer.

Abstract: Tunnel field-effect transistors are provided. A tunnel field-effect transistor (TFET) includes a semiconductor substrate; a gate structure having a first side and an opposing second side formed on the semiconductor substrate. A first doped source/drain layer is formed in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and a channel region of the semiconductor substrate has a plurality of protruding structures protruding toward the channel region under the gate structure. A second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductive type opposite to the first source/drain doping layer.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes forming a first type of fin sidewall spacers and a second type of fin sidewall spacers. The first type of fin sidewall spacers are formed on two sidewall surfaces of a third fin portion group along a width direction of the third fin portions and two sidewall surfaces of a fourth fin portion group along a width direction of the fourth fin portions. The second type of fin sidewall spacers are formed between adjacent third fin portions and sidewall surfaces of the third fin portions and between adjacent fourth fin portions and on sidewall surfaces of the fourth fin portions. Top surfaces of the first type of fin sidewall spacers are higher than top surfaces of the second type of fin sidewall spacers and top surfaces of the third fin portions and the fourth fin portions.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming at least one gate structure having a gate dielectric layer on a surface of the semiconductor substrate; forming first sidewall spacers on a first sidewall surface region of the gate structure and covering sidewall surfaces of the gate dielectric layer; forming second sidewall spacers on a second sidewall surface region of the gate structure and top surfaces of the first sidewall spacers and made of a material different from a material of the first sidewall spacers; forming conductive plugs in the dielectric layer at both sides of the gate structure, the first sidewall spacers and the second sidewall spacers; and removing the second sidewall spacers to form air gap spacers above the first sidewall spacers and between the second sidewall surface region of the gate structure and the conductive plugs.

Abstract: Tunnel field-effect transistors and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a gate structure having a first side and an opposing second side on the semiconductor substrate; and forming a first doped source/drain layer in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and the channel region has protruding structures protruding toward a channel region under the gate structure. The method also includes forming a second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductivity opposite to the first doped source/drain layer.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure on a top surface of the base substrate; and forming a first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the first doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a first distance. The method also includes forming a second doped source/drain layer on the first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the second doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a second distance; and the second distance is greater than the first distance.

Abstract: The present specification discloses a semiconductor device and a method for manufacturing same.