Patents by Inventor Poren Tang
Poren Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190181241Abstract: This application discloses a gate-all-around field effect transistor and a method for manufacturing same.Type: ApplicationFiled: November 6, 2018Publication date: June 13, 2019Applicants: Semiconductor Manufacturing International (Beijing) Corporation, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventor: Poren Tang
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Publication number: 20190035892Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure on a top surface of the base substrate; and forming a first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the first doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a first distance. The method also includes forming a second doped source/drain layer on the first doped source/drain layer at both sides of the gate structure. A minimum distance between a sidewall surface of the second doped source/drain doping layer and an adjacent sidewall surface of the gate structure is a second distance; and the second distance is greater than the first distance.Type: ApplicationFiled: July 23, 2018Publication date: January 31, 2019Inventor: Poren TANG
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Publication number: 20190019865Abstract: Tunnel field-effect transistors and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a gate structure having a first side and an opposing second side on the semiconductor substrate; and forming a first doped source/drain layer in the semiconductor substrate at the first side of the gate structure. The first doped source/drain layer is doped with a first type of doping ions and a first contact interface between the first doped source/drain layer and the channel region has protruding structures protruding toward a channel region under the gate structure. The method also includes forming a second doped source/drain layer in the semiconductor substrate at the second side of the gate structure. The second doped source/drain layer is doped with a second type of doping ions having a conductivity opposite to the first doped source/drain layer.Type: ApplicationFiled: July 16, 2018Publication date: January 17, 2019Inventor: Poren TANG
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Patent number: 10008575Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern. The first spacer is between the first wire pattern and the substrate, and the first spacer is between the gate insulating layer and the semiconductor pattern.Type: GrantFiled: October 20, 2016Date of Patent: June 26, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Chan Suh, Yong Suk Tak, Gi Gwan Park, Mi Seon Park, Moon Seung Yang, Seung Hun Lee, Poren Tang
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Patent number: 9899272Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.Type: GrantFiled: August 11, 2016Date of Patent: February 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Poren Tang, Sunjung Steve Kim, Moon Seung Yang, Seung Hun Lee, Hyun Jung Lee, Geun Hee Jeong
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Publication number: 20170222006Abstract: A semiconductor device includes at least a first wire pattern, a gate electrode, a semiconductor pattern, a gate insulating layer, and a first spacer. The first wire pattern is on a substrate and isolated from the substrate. The gate electrode surrounds and intersects the first wire pattern. The semiconductor pattern is on both sides of the first wire pattern, and the semiconductor pattern includes a portion which overlaps the first wire pattern. The gate insulating layer is disposed between the gate electrode and the first wire pattern, and the gate insulating layer surrounds the first wire pattern.Type: ApplicationFiled: October 20, 2016Publication date: August 3, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Dong Chan SUH, Yong Suk TAK, Gi Gwan PARK, Mi Seon PARK, Moon Seung YANG, Seung Hun LEE, Poren TANG
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Publication number: 20170092547Abstract: Methods of fabricating semiconductor device are provided including forming first and second material layers for a first transistor using epitaxial growth processes. A recess region is formed by partially etching the first and second material layers. Third and fourth material layers for a second transistor are formed using epitaxial growth processes.Type: ApplicationFiled: August 11, 2016Publication date: March 30, 2017Inventors: Poren Tang, Sunjung Steve KIM, Moon Seung YANG, Seung Hun LEE, Hyun Jung LEE, Geun Hee JEONG
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Patent number: 9508832Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.Type: GrantFiled: June 24, 2015Date of Patent: November 29, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Jung Lee, Bonyoung Koo, Sunjung Kim, Jongryeol Yoo, Seung Hun Lee, Poren Tang
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Publication number: 20160056269Abstract: A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.Type: ApplicationFiled: June 24, 2015Publication date: February 25, 2016Inventors: Hyun Jung LEE, Bonyoung KOO, Sunjung KIM, Jongryeol YOO, Seung Hun LEE, Poren TANG
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Patent number: 8942036Abstract: The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.Type: GrantFiled: October 14, 2011Date of Patent: January 27, 2015Assignee: Peking UniversityInventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Yu Tang, Shenghu Tan, Xin Huang, Yue Pan
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Publication number: 20140145139Abstract: The present invention discloses a transparent flexible resistive memory and a fabrication method thereof. The transparent flexible resistive memory includes a transparent flexible substrate, a memory unit with a MIM capacitor structure over the substrate, wherein a bottom electrode and a top electrode of the memory unit are transparent and flexible, and an intermediate resistive layer is a transparent flexible film of poly(p-xylylene). Poly(p-xylylene) has excellent resistive characteristics. In the device, the substrate, the electrodes and the intermediate resistive layer are all formed of transparent flexible material so that a completely transparent flexible resistive memory which can be used in a transparent flexible electronic system is obtained.Type: ApplicationFiled: February 22, 2012Publication date: May 29, 2014Inventors: Ru Huang, Yu Tang, Yimao Cai, Lijie Zhang, Gengyu Yang, Shenghu Tan, Yue Pan, Poren Tang
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Patent number: 8593848Abstract: The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.Type: GrantFiled: April 21, 2011Date of Patent: November 26, 2013Assignee: Peking UniversityInventors: Yimao Cai, Ru Huang, Poren Tang, Shiqiang Qin
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Patent number: 8526242Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process.Type: GrantFiled: March 7, 2011Date of Patent: September 3, 2013Assignee: Peking UniversityInventors: Ru Huang, Yimao Cai, Shiqiang Qin, Qianqian Huang, Poren Tang, Yu Tang, Gengyu Yang
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Publication number: 20120261740Abstract: The present invention discloses a flash memory and a method for fabricating the same, and relates to the technical field of the semiconductor memory. The flash memory includes a buried oxygen layer on which a source terminal, a channel, and a drain terminal are disposed, wherein the channel is between the source terminal and the drain terminal, and a tunneling oxide layer, a polysilicon floating gate, a blocking oxide layer, and a polysilicon control gate are sequentially disposed on the channel, and a thin silicon nitride layer is disposed between the source terminal and the channel.Type: ApplicationFiled: October 14, 2011Publication date: October 18, 2012Applicant: PEKING UNIVERSITYInventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Shenghu Tan
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Publication number: 20120243313Abstract: The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.Type: ApplicationFiled: April 21, 2011Publication date: September 27, 2012Inventors: Yimao Cai, Ru Huang, Poren Tang, Shiqiang Qin
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Publication number: 20120188821Abstract: The present invention discloses a method for achieving four-bit storage by using a flash memory having a splitting trench gate. The flash memory with the splitting trench gate is disclosed in a Chinese patent No. 200710105964.2. At one side that each of two trenches is contacted with a channel, a programming for electrons is achieved by using a channel hot electron injection method; and at the other side that each of the two trenches is contacted with a source or a drain, a programming for electrons is achieved by using an FN injection method, so that a function of a four-bit storage of the device is achieved by changing a programming mode. Thus, a performance of the device is improved while a storage density is greatly increased.Type: ApplicationFiled: October 14, 2011Publication date: July 26, 2012Inventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, Yu Tang, Shenghu Tan, Xin Huang, Yue Pan
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Publication number: 20120113726Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process.Type: ApplicationFiled: March 7, 2011Publication date: May 10, 2012Applicant: PEKING UNIVERSITYInventors: Ru Huang, Yimao Cai, Shiqiang Qin, Qianqian Huang, Poren Tang, Yu Tang, Gengyu Yang
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Publication number: 20120099381Abstract: The present invention discloses an embedded non-volatile memory cell, an operation method and a memory array thereof. The method includes using a gate of a selection transistor as a floating gate of a memory, and using a source electrode and a drain electrode of the selection transistor as a source electrode and a drain electrode of the memory; and then changing a threshold of the device by varying the electrode voltages, thereby realizing a storage and change of information. The invention has advantages of a small area, a low operating voltage, high operating speed and high reliability.Type: ApplicationFiled: May 19, 2011Publication date: April 26, 2012Applicant: PEKING UNIVERSITYInventors: Yimao Cai, Poren Tang, Ru Huang, Xiaoyan Xu
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Publication number: 20120061637Abstract: The present invention relates to a field of nonvolatile memory technology in ULSI circuits manufacturing technology and discloses a 3D-structured resistive-switching memory array and a method for fabricating the same.Type: ApplicationFiled: April 1, 2011Publication date: March 15, 2012Inventors: Yimao Cai, Ru Huang, Shiqiang Qin, Poren Tang, LIjie Zhang, Yu Tang