Patents by Inventor Prabhat Agarwal

Prabhat Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11928629
    Abstract: A method, computer system, and a computer program product for anomaly detection is provided. The present invention may include converting business process logs into a graphical data structure. The present invention may include generating an optimized graph encoding for anomaly detection using an unsupervised machine learning model. The present invention may include computing an anomaly score for each activity of the business process log using a process aware metric based on feature representation. The present invention may include labeling each of the one or more data points with a high anomaly score.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: March 12, 2024
    Assignee: International Business Machines Corporation
    Inventors: Siyu Huo, Prabhat Maddikunta Reddy, Vatche Isahagian, Vinod Muthusamy, Prerna Agarwal
  • Patent number: 9231201
    Abstract: The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: January 5, 2016
    Assignee: NXP B.V.
    Inventors: Robertus Theodorus Fransiscus Van Schaijk, Prabhat Agarwal, Erik Petrus Antonius Maria Bakkers, Martijn Henri Richard Lankhorst, Michiel Jos Van Duuren, Abraham Rudolf Balkenende, Louis Felix Feiner, Pierre Hermanus Woerlee
  • Patent number: 8330090
    Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).
    Type: Grant
    Filed: April 29, 2008
    Date of Patent: December 11, 2012
    Assignee: NXP, B.V.
    Inventor: Prabhat Agarwal
  • Patent number: 8159018
    Abstract: A finFET-based non-volatile memory device on a semiconductor substrate includes source and drain regions, a fin body, a charge trapping stack and a gate. The fin body extends between the source and the drain region as a connection. The charge trapping stack covers a portion of the fin body and the gate covers the charge trapping stack at the location of the fin body. The fin body has a corner-free shape for at least ¾ of the circumference of the fin body which lacks distinct crystal faces and transition zones in between the crystal faces.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: April 17, 2012
    Assignee: NXP B.V.
    Inventors: Nader Akil, Prabhat Agarwal, Robertus T. F. Van Schaijk
  • Patent number: 8134142
    Abstract: The invention suggests a transistor (21) comprising a source (24) and a drain (29) as well as a barrier region (27) located between the source and the drain. The barrier region is separated from the source and the drain by intrinsic or lowly doped regions (26, 28) of a semiconductor material. Potential barriers are formed at the interfaces of the barrier region and the intrinsic or lowly doped regions. A gate electrode (32) is provided in the vicinity of the potential barriers such that the effective height and/or width of the potential barriers can be modulated by applying an appropriate voltage to the gate electrode.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: March 13, 2012
    Assignee: NXP B.V.
    Inventors: Godefridus Hurkx, Prabhat Agarwal
  • Patent number: 7989844
    Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Rob Van Dalen, Prabhat Agarwal, Jan Willem Slotboom, Gerrit Elbert Johannes Koops
  • Patent number: 7939854
    Abstract: The invention relates to a semiconductor device with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region comprises a mixed crystal of silicon and germanium, the base region is separated from the emitter region by an intermediate region of silicon having a doping concentration which is lower than the doping concentration of the emitter region and with a thickness smaller than the thickness of the emitter region, and the emitter region comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region remote from the intermediate region.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: May 10, 2011
    Assignee: NXP, B.V.
    Inventors: Philippe Meunier-Beillard, Raymond James Duffy, Prabhat Agarwal, Godfridus Adrianus Maria Hurkx
  • Patent number: 7915709
    Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 29, 2011
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Prabhat Agarwal, Abraham Rudolf Balkenende, Petrus Hubertus Cornelis Magnee, Melanie Maria Hubertina Wagemans, Erik Petrus Antonius Maria Bakkers, Erwin Hijzen
  • Publication number: 20110018065
    Abstract: A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20?) obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20?); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20? may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.
    Type: Application
    Filed: February 17, 2009
    Publication date: January 27, 2011
    Applicant: NXP B.V.
    Inventors: Gilberto Curatola, Prabhat Agarwal, Mark J. H. Van Dal, Vijayaraghavan Madakasira
  • Patent number: 7868424
    Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) comprising a vertical bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type and the first conductivity type, wherein the collector region (3) comprises a first sub-region (3A) bordering the base region (2) and a second sub-region (3B) bordering the first sub-region (3A) which has a lower doping concentration than the second sub-region (3B), and the transistor is provided with a gate electrode (5) which laterally borders the first sub-region (3A) and by means of which the first sub-region (3A) may be depleted.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 11, 2011
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Prabhat Agarwal, Erwin Hijzen, Raymond Josephus Engelbart Hueting
  • Patent number: 7839209
    Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: November 23, 2010
    Assignee: NXP B.V.
    Inventors: Gilberto Curatola, Prabhat Agarwal, Jan W. Slotboom, Godefridus A. M. Hurkx, Radu Surdeanu, Gerben Doornbos
  • Patent number: 7838368
    Abstract: A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 23, 2010
    Assignee: NXP B.V.
    Inventors: Radu Surdeanu, Prabhat Agarwal, Abraham Rudolf Balkenende, Erik P. A. M. Bakkers
  • Patent number: 7791108
    Abstract: A transistor comprises a nanowire (22, 22?) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: September 7, 2010
    Assignee: NXP B.V.
    Inventors: Fred Hurkx, Prabhat Agarwal
  • Patent number: 7759650
    Abstract: A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n-doped region (16) disposed adjacent to the substrate (14), and a p-doped region (18) disposed adjacent to the n-doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p-doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p-doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n-doped region.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: July 20, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Anco Heringa, Thomas Frach, Prabhat Agarwal
  • Publication number: 20100127153
    Abstract: A photosensitive device (100), the photosensitive device (100) comprising a substrate (101) and a plurality of vertically aligned nanowire diodes (102 to 105) provided on and/or in the substrate (101).
    Type: Application
    Filed: April 28, 2008
    Publication date: May 27, 2010
    Applicant: NXP B.V.
    Inventor: Prabhat Agarwal
  • Patent number: 7714292
    Abstract: A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: May 11, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Prabhat Agarwal, Jan Sonsky, Lasse Juhana Kauppinen
  • Patent number: 7709923
    Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
    Type: Grant
    Filed: October 29, 2006
    Date of Patent: May 4, 2010
    Assignee: NXP B.V.
    Inventors: Prabhat Agarwal, Godefridus A. M. Hurkx
  • Publication number: 20100097135
    Abstract: A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
    Type: Application
    Filed: October 3, 2007
    Publication date: April 22, 2010
    Applicant: NXP, B.V.
    Inventors: Gilberto Curatola, Prabhat Agarwal, Jan W. Slotboom, Godefridus A.M. Hurkx, Radu Surdeanu
  • Patent number: 7671447
    Abstract: The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) of, respectively, a first conductivity type, a second conductivity type, opposite to the first conductivity type, and the first conductivity type, wherein, viewed in projection, the emitter region (1) is positioned above or below the base region (2), and the collector region (3) laterally borders the base region (2). According to the invention, the base region (2) comprises a highly doped subregion (2A) the doping concentration of which has a delta-shaped profile in the thickness direction, and said highly doped sub-region (2A) extends laterally as far as the collector region (3). Such a lateral bipolar transistor has excellent high-frequency properties and a relatively high breakdown voltage between the base and collector regions (2, 3), implying that the device is suitable for high power applications.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: March 2, 2010
    Assignee: NXP B.V.
    Inventors: Andreas Hubertus Montree, Jan Willem Slotboom, Prabhat Agarwal, Philippe Meunier-Beillard
  • Patent number: 7667502
    Abstract: There is provided a LVDS driver arranged to receive an input signal which switches between two voltage levels. The driver comprises a pre-emphasis block (405) for generating a pre-emphasis signal having a first voltage level for a time period T1 after each switch of the input signal, and a second voltage level at all other times, a differential pair of outputs for generating a differential output voltage across a load resistor (RI); and a driver circuit (401) comprising two parallel branches, each branch being connected to one output and each branch being arranged to receive the pre-emphasis signal.
    Type: Grant
    Filed: November 4, 2005
    Date of Patent: February 23, 2010
    Assignee: Infineon Technologies AG
    Inventor: Prabhat Agarwal