Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

Abstract: Computer-implemented methods, computer program products, and computer systems for testing a voice assistant device may include one or more processors configured for receiving test data from a database, wherein the test data may include a first set of coding parameters and a first user utterance having an expected device response. Further, the one or more processors may be configured for generating a first modified user utterance by applying the first set of coding parameters to the first user utterance, wherein the first modified user utterance is acoustically different than the first user utterance. The one or more processors may be configured for audibly presenting the first modified user utterance to a voice assistant device, receiving a first device response from the voice assistant device, and determining whether the first voice assistant response is substantially similar to the expected device response.

Abstract: One implementation includes a random access memory (RAM) that has a muted multiplexing functionality. For instance, a RAM may be implemented having a first outer bank, a first inner bank, a second outer bank, and a second inner bank, each coupled to a controller. Multiplexing circuits for the outer banks may be disposed adjacent the outer banks and away from the controller, whereas the multiplexing circuits for the inner banks may be disposed within or adjacent to the controller.

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

Abstract: A computer-implemented method for sender activated mobile call overloading (SAMCO) is described that includes processors configured for receiving request call data comprising a data request initiated by a sending mobile device intended for a receiving mobile device, receiving active call data corresponding to a telephone call placed by the sending mobile device to the receiving mobile device, wherein the active call data comprises the data request, determining that the receiving mobile device is subscribed to a data request service configured to execute the data request, determining that the sending mobile device is authorized to access the receiving mobile device, and responsive to determining that the sending mobile device is authorized, the method includes processors configured for transmitting the data request to the receiving mobile device.

Abstract: Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

Abstract: A computer implemented method manages zero-day vulnerabilities in an application package having a set of components. The computer ingests data about potential vulnerabilities from a plurality of data sources. Using a set of machine learning models, the computer predicts a vulnerability based on of the data that was ingested. The computer performs a code analysis of the set of components to identify a possibility of the vulnerability impacting the application package. The computer generates a recommendation to resolve the vulnerability based on the code analysis and the data that was ingested. The computer manages the recommendation in a private blockchain.

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

Abstract: A system, method, and computer program product for implementing microservice deployment is provided. The method includes receiving definitions associated with microservices related to implementing hardware and software solutions with respect to hardware and software systems. In response, a definition file and associated code comprising the definitions and associated dependencies associated with the microservices are generated. The microservices are deployed to a container orchestration system cluster on a cloud structure and a service mesh and machine learning module are installed within the container orchestration system cluster. Proxies comprising a proxy for each pair of dependencies are generated and network traffic passing through each proxy is monitored. A malfunction of a hardware or software system is detected and an associated network route passing through an associated proxy is disabled.

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: Embodiments of the present invention provide a computer system a computer program product, and a method that comprises converting the retrieved data to a uniform syntax for data assessment; performing a query on a plurality of external data sources for additional information associated with the converted data; analyzing a plurality of indicative markers associated with the retrieved data and the additional information; generating a plurality of machine learning models associated with the converted data based on the analysis of each indicative markers within the plurality of indicative markers; dynamically selecting at least one generated machine learning model within the plurality of generated machine learning models associated with the retrieved data based on an analysis of the plurality of indicative markers associated with the retrieved data and the additional information; and automatically verifying an accuracy value associated with the at least one selected generated machine learning model.

Abstract: Computer-implemented methods, computer program products, and computer systems for testing a voice assistant device may include one or more processors configured for receiving test data from a database, wherein the test data may include a first set of coding parameters and a first user utterance having an expected device response. Further, the one or more processors may be configured for generating a first modified user utterance by applying the first set of coding parameters to the first user utterance, wherein the first modified user utterance is acoustically different than the first user utterance. The one or more processors may be configured for audibly presenting the first modified user utterance to a voice assistant device, receiving a first device response from the voice assistant device, and determining whether the first voice assistant response is substantially similar to the expected device response.

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

Abstract: A memory and method of performing a write operation in a memory are disclosed. In one aspect of the disclosure, the memory includes a memory cell, a pair of bit lines coupled to the memory cell, a multiplexer, and a pull-up circuit coupled to the multiplexer. The multiplexer may be configured to select the pair of bit lines coupled to the memory cell during the write operation. To increase the write performance of the memory cell, the pull-up circuit is configured to select which of the pair of bit lines is a non-zero bit line during the write operation and to clamp the non-zero bit line through the multiplexer to approximately a power rail voltage. Thus, the pull-up circuit may increase the voltage difference between the non-zero bit line and the zero bit line during the write operation and thus decrease the area and power consumed by a boost capacitance.

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.